Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Gate and inverter XOR gate 74HC TSSOP 8

1. General description

The 74HC2G86; 74HCT2G86 is a dual 2-input EXCLUSIVE-OR gate. Inputs include

clamp diodes that enable the use of current limiting resistors to interface inputs to voltages

in excess of V

2. Features and benefits

 Wide supply voltage range from 2.0 V to 6.0 V

 Input levels:

 For 74HC2G86: CMOS level

 For 74HCT2G86: TTL level

 Symmetrical output impedance

 High noise immunity

 Low power dissipation

 Balanced propagation delays

 Multiple package options

 ESD protection:

 HBM JESD22-A114E exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V

 Specified from 40 C to +85 C and 40 C to +125 C

3. Ordering information

74HC2G86; 74HCT2G86

Dual 2-input EXCLUSIVE-OR gate

Rev. 4 — 14 March 2014 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74HC2G86DP 40 C to +125 C TSSOP8 plastic thin shrink small outline package; 8 leads;

body width 3 mm; lead length 0.5 mm

SOT505-2

74HCT2G86DP

74HC2G86DC 40 C to +125 C VSSOP8 plastic very thin shrink small outline package; 8 leads;

body width 2.3 mm

SOT765-1

74HCT2G86DC

74HC2G86GD 40 C to +125 C XSON8 plastic extremely thin small outline package; no leads;

8 terminals; body 3  2  0.5 mm

SOT996-2

74HCT2G86GD

Summary of content (15 pages)

PAGE 1
74HC2G86; 74HCT2G86 Dual 2-input EXCLUSIVE-OR gate Rev. 4 — 14 March 2014 Product data sheet 1. General description The 74HC2G86; 74HCT2G86 is a dual 2-input EXCLUSIVE-OR gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits  Wide supply voltage range from 2.0 V to 6.
PAGE 2
74HC2G86; 74HCT2G86 NXP Semiconductors Dual 2-input EXCLUSIVE-OR gate 4. Marking Table 2. Marking code Type number Marking code[1] 74HC2G86DP H86 74HCT2G86DP T86 74HC2G86DC H86 74HCT2G86DC T86 74HC2G86GD H86 74HCT2G86GD T86 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram =1 1A 1B 1Y 2A 2B 2Y =1 001aah760 Fig 1. 001aah761 Logic symbol Fig 2. IEC logic symbol B Y A Fig 3.
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74HC2G86; 74HCT2G86 NXP Semiconductors Dual 2-input EXCLUSIVE-OR gate 6. Pinning information 6.1 Pinning 74HC2G86 74HCT2G86 74HC2G86 74HCT2G86 1A 1 8 VCC 1B 2 7 1Y 2Y 3 6 2B GND 4 5 2A 1A 1 8 VCC 1B 2 7 1Y 2Y 3 6 2B GND 4 5 2A 001aak027 Transparent top view 001aak026 Fig 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) Fig 5. Pin configuration SOT996-2 (XSON8) 6.2 Pin description Table 3.
PAGE 4
74HC2G86; 74HCT2G86 NXP Semiconductors Dual 2-input EXCLUSIVE-OR gate 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VCC supply voltage Min Max Unit 0.5 +7.0 V IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V [1] - 20 mA IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] - 20 mA output current VO = 0.
PAGE 5
74HC2G86; 74HCT2G86 NXP Semiconductors Dual 2-input EXCLUSIVE-OR gate Table 7. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIL VOH VOL LOW-level input voltage 25 C Conditions VCC = 2.0 V 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.
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74HC2G86; 74HCT2G86 NXP Semiconductors Dual 2-input EXCLUSIVE-OR gate 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 7. Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V - 34 120 - 150 - 180 ns VCC = 4.5 V - 11 20 - 25 - 36 ns - 9.0 17 - 21 - 30 ns VCC = 2.0 V - 18 75 - 95 - 110 ns VCC = 4.
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4HC2G86; 74HCT2G86 NXP Semiconductors Dual 2-input EXCLUSIVE-OR gate 12. Waveforms VI nA, nB input VM GND tPHL VOH VM VX nY output VOL tPLH VY tTHL tTLH 001aak020 Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig 6. Propagation delay data input (nA, nB) to data output (nY) and transition time output (nY) Table 9. Measurement points Type Input Output VM VM VX VY 74HC2G86 0.5VCC 0.5VCC 0.1VCC 0.
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74HC2G86; 74HCT2G86 NXP Semiconductors Dual 2-input EXCLUSIVE-OR gate VI tW 90 % negative pulse VM 0V VI tf tr tr tf 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC VCC VI G VO RL S1 open DUT CL RT 001aad983 Test data is given in Table 10. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 7.
PAGE 9
74HC2G86; 74HCT2G86 NXP Semiconductors Dual 2-input EXCLUSIVE-OR gate 13. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm D E A SOT505-2 X c HE y v M A Z 5 8 A A2 (A3) A1 pin 1 index θ Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.00 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.
PAGE 10
74HC2G86; 74HCT2G86 NXP Semiconductors Dual 2-input EXCLUSIVE-OR gate VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D E SOT765-1 A X c y HE v M A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 4 e L detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1 0.15 0.00 0.85 0.60 0.12 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.5 3.2 3.0 0.4 0.
PAGE 11
74HC2G86; 74HCT2G86 NXP Semiconductors Dual 2-input EXCLUSIVE-OR gate XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 3 x 2 x 0.5 mm B D SOT996-2 A E A A1 detail X terminal 1 index area e1 1 4 8 5 C C A B C v w b e L1 y y1 C L2 L X 0 1 2 mm scale Dimensions (mm are the original dimensions) Unit(1) max nom min mm A A1 b 0.05 0.35 D E 2.1 3.1 0.5 0.00 0.15 1.9 e e1 0.5 1.5 2.9 L L1 L2 0.5 0.15 0.6 0.3 0.05 0.4 v 0.
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74HC2G86; 74HCT2G86 NXP Semiconductors Dual 2-input EXCLUSIVE-OR gate 14. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT2G86 v.4 20140314 Product data sheet - 74HC_HCT2G86 v.
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74HC2G86; 74HCT2G86 NXP Semiconductors Dual 2-input EXCLUSIVE-OR gate 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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74HC2G86; 74HCT2G86 NXP Semiconductors Dual 2-input EXCLUSIVE-OR gate Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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NXP Semiconductors 74HC2G86; 74HCT2G86 Dual 2-input EXCLUSIVE-OR gate 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . .