Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Latch Transparent D latch Three-state SOIC 20

1. General description

The 74HC373-Q100; 74HCT373-Q100 is a high-speed Si-gate CMOS device and is pin

compatible with Low-power Schottky TTL. It is specified in compliance with JEDEC

standard no. 7A.

The 74HC373-Q100; 74HCT373-Q100 is an octal D-type transparent latch featuring

separate D-type inputs for each latch and 3-state outputs for bus-oriented applications. A

latch enable (LE) input and an output enable (OE

) input are common to all latches.

The 74HC373-Q100; 74HCT373-Q100 consists of eight D-type transparent latches with

3-state true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this

condition the latches are transparent, i.e. a latch output changes state each time its

corresponding D input changes.

When LE is LOW, the latches store the information that was present at the D inputs a

set-up time preceding the HIGH-to-LOW transition of LE. When OE

is LOW, the contents

of the 8 latches are available at the outputs. When OE

is HIGH, the outputs go to the high-

impedance OFF-state. Operation of the OE

input does not affect the state of the latches.

The 74HC373-Q100; 74HCT373-Q100 is functionally identical to:

• 74HC573-Q100; 74HCT573-Q100: but different pin arrangement

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +85 C and from 40 C to +125 C

 Input levels:

 For 74HC373-Q100: CMOS level

 For 74HCT373-Q100: TTL level

 3-state non-inverting outputs for bus-oriented applications

 Common 3-state output enable input

 Functionally identical to the 74HC573-Q100; 74HCT573-Q100

 ESD protection:

 MIL-STD-883, method 3015 exceeds 2000 V

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )

 Multiple package options

74HC373-Q100; 74HCT373-Q100

Octal D-type transparent latch; 3-state

Rev. 1 — 10 August 2012 Product data sheet

Summary of content (24 pages)

PAGE 1
74HC373-Q100; 74HCT373-Q100 Octal D-type transparent latch; 3-state Rev. 1 — 10 August 2012 Product data sheet 1. General description The 74HC373-Q100; 74HCT373-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A. The 74HC373-Q100; 74HCT373-Q100 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus-oriented applications.
PAGE 2
74HC373-Q100; 74HCT373-Q100 NXP Semiconductors Octal D-type transparent latch; 3-state 3. Ordering information Table 1. Ordering information Type number Package 74HC373D-Q100 Temperature range Name Description Version 40 C to +125 C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.
PAGE 3
74HC373-Q100; 74HCT373-Q100 NXP Semiconductors Octal D-type transparent latch; 3-state LE LE LE D Q LE Fig 4. 001aae051 Logic diagram (one latch) D0 D1 D Q D2 D Q D3 D Q D4 D Q D5 D Q D6 D Q D7 D Q D Q LATCH 1 LATCH 2 LATCH 3 LATCH 4 LATCH 5 LATCH 6 LATCH 7 LATCH 8 LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 001aae052 Fig 5.
PAGE 4
74HC373-Q100; 74HCT373-Q100 NXP Semiconductors Octal D-type transparent latch; 3-state 5. Pinning information 5.
PAGE 5
74HC373-Q100; 74HCT373-Q100 NXP Semiconductors Octal D-type transparent latch; 3-state 6. Functional description 6.1 Function table Table 3.
PAGE 6
NXP Semiconductors 74HC373-Q100; 74HCT373-Q100 Octal D-type transparent latch; 3-state 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC373-Q100 Min Typ 74HCT373-Q100 Max Min Typ Unit Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.
PAGE 7
NXP Semiconductors 74HC373-Q100; 74HCT373-Q100 Octal D-type transparent latch; 3-state Table 6. Static characteristics 74HC373-Q100 …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VCC = 2.0 V 1.5 - - V VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V VCC = 2.0 V - - 0.5 V VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V IO = 20 A; VCC = 2.0 V 1.9 - - V IO = 20 A; VCC = 4.
PAGE 8
NXP Semiconductors 74HC373-Q100; 74HCT373-Q100 Octal D-type transparent latch; 3-state Table 6. Static characteristics 74HC373-Q100 …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VOL LOW-level output voltage VI = VIH or VIL IO = 20 A; VCC = 2.0 V - - 0.1 V IO = 20 A; VCC = 4.5 V - - 0.1 V IO = 20 A; VCC = 6.0 V - - 0.1 V IO = 6.0 mA; VCC = 4.5 V - - 0.4 V IO = 7.8 mA; VCC = 6.
PAGE 9
NXP Semiconductors 74HC373-Q100; 74HCT373-Q100 Octal D-type transparent latch; 3-state Table 7. Static characteristics 74HCT373-Q100 …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VOH HIGH-level output voltage VI = VIH or VIL VOL LOW-level output voltage Min Typ Max Unit IO = 20 A; VCC = 4.5 V 4.4 - - V IO = 6.0 A; VCC = 4.5 V 3.84 - - V IO = 20 A; VCC = 4.5 V - - 0.1 V IO = 6.0 mA; VCC = 4.
PAGE 10
74HC373-Q100; 74HCT373-Q100 NXP Semiconductors Octal D-type transparent latch; 3-state 10. Dynamic characteristics Table 8. Dynamic characteristics 74HC373-Q100 Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter Conditions Min Typ Max Unit VCC = 2.0 V - 41 150 ns VCC = 4.5 V - 15 30 ns VCC = 5 V; CL = 15 pF - 12 - ns VCC = 6.0 V - 12 26 ns VCC = 2.0 V - 50 175 ns VCC = 4.
PAGE 11
NXP Semiconductors 74HC373-Q100; 74HCT373-Q100 Octal D-type transparent latch; 3-state Table 8. Dynamic characteristics 74HC373-Q100 …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter Conditions Min Typ Max Unit Tamb = 40 C to +85 C tpd propagation delay Dn to Qn; see Figure 8 [1] VCC = 2.0 V - - 190 ns VCC = 4.5 V - - 38 ns VCC = 6.0 V - - 33 ns VCC = 2.0 V - - 220 ns VCC = 4.
PAGE 12
NXP Semiconductors 74HC373-Q100; 74HCT373-Q100 Octal D-type transparent latch; 3-state Table 8. Dynamic characteristics 74HC373-Q100 …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter Conditions Min Typ Max Unit Tamb = 40 C to +125 C tpd propagation delay Dn to Qn; see Figure 8 [1] VCC = 2.0 V - - 225 ns VCC = 4.5 V - - 45 ns VCC = 6.0 V - - 38 ns VCC = 2.0 V - - 265 ns VCC = 4.
PAGE 13
NXP Semiconductors 74HC373-Q100; 74HCT373-Q100 Octal D-type transparent latch; 3-state Table 8. Dynamic characteristics 74HC373-Q100 …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter Conditions th Dn to LE; see Figure 11 [1] hold time Min Typ Max Unit VCC = 2.0 V 5 - - ns VCC = 4.5 V 5 - - ns VCC = 6.0 V 5 - - ns tpd is the same as tPLH and tPHL. [2] ten is the same as tPZH and tPZL.
PAGE 14
NXP Semiconductors 74HC373-Q100; 74HCT373-Q100 Octal D-type transparent latch; 3-state Table 9. Dynamic characteristics 74HCT373-Q100 …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
PAGE 15
74HC373-Q100; 74HCT373-Q100 NXP Semiconductors Octal D-type transparent latch; 3-state Table 9. Dynamic characteristics 74HCT373-Q100 …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter Conditions th Dn to LE; see Figure 11 hold time Dn to LE VCC = 4.5 V [1] tpd is the same as tPLH and tPHL. [2] ten is the same as tPZH and tPZL. [3] tdis is the same as tPLZ and tPHZ.
PAGE 16
74HC373-Q100; 74HCT373-Q100 NXP Semiconductors Octal D-type transparent latch; 3-state VI OE input VM GND tPLZ tPZL VCC output LOW-to-OFF OFF-to-LOW VM 10% VOL tPHZ tPZH VOH 90% output HIGH-to-OFF OFF-to-HIGH GND VM outputs enabled outputs disabled outputs enabled 001aae307 Measurement points are given in Table 10. Fig 10. 3-state enable and disable time VM LE input t su t su th th VM Dn input 001aae084 Measurement points are given in Table 10. Fig 11.
PAGE 17
74HC373-Q100; 74HCT373-Q100 NXP Semiconductors Octal D-type transparent latch; 3-state VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC VCC G VI VO RL S1 open DUT CL RT 001aad983 Test data is given in Table 11.
PAGE 18
74HC373-Q100; 74HCT373-Q100 NXP Semiconductors Octal D-type transparent latch; 3-state 12. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 10 1 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.
PAGE 19
74HC373-Q100; 74HCT373-Q100 NXP Semiconductors Octal D-type transparent latch; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.
PAGE 20
74HC373-Q100; 74HCT373-Q100 NXP Semiconductors Octal D-type transparent latch; 3-state DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 9 y y1 C v M C A B w M C b L 1 10 Eh e 20 11 19 12 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b 1 0.05 0.00 0.30 0.
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74HC373-Q100; 74HCT373-Q100 NXP Semiconductors Octal D-type transparent latch; 3-state 13. Abbreviations Table 12. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic MIL Military 14. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT373_Q100 v.
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74HC373-Q100; 74HCT373-Q100 NXP Semiconductors Octal D-type transparent latch; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
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NXP Semiconductors 74HC373-Q100; 74HCT373-Q100 Octal D-type transparent latch; 3-state No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only.
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NXP Semiconductors 74HC373-Q100; 74HCT373-Q100 Octal D-type transparent latch; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 6.1 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning .