Datasheet

74HC_HCT373_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 10 August 2012 10 of 24
NXP Semiconductors
74HC373-Q100; 74HCT373-Q100
Octal D-type transparent latch; 3-state
10. Dynamic characteristics
Table 8. Dynamic characteristics 74HC373-Q100
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter Conditions Min Typ Max Unit
T
amb
=25C
t
pd
propagation delay Dn to Qn; see Figure 8
[1]
V
CC
= 2.0 V - 41 150 ns
V
CC
= 4.5 V - 15 30 ns
V
CC
=5V; C
L
=15pF - 12 - ns
V
CC
= 6.0 V - 12 26 ns
LE to Qn; see Figure 9
V
CC
= 2.0 V - 50 175 ns
V
CC
= 4.5 V - 18 35 ns
V
CC
=5V; C
L
=15pF - 15 - ns
V
CC
= 6.0 V - 14 30 ns
t
en
enable time OE to Qn; see Figure 10
[2]
V
CC
= 2.0 V - 44 150 ns
V
CC
= 4.5 V - 16 30 ns
V
CC
= 6.0 V - 13 26 ns
t
dis
disable time OE to Qn; see Figure 10
[3]
V
CC
= 2.0 V - 47 150 ns
V
CC
= 4.5 V - 17 30 ns
V
CC
= 6.0 V - 14 26 ns
t
t
transition time Qn; see Figure 8 and Figure 9
[4]
V
CC
= 2.0 V - 14 60 ns
V
CC
= 4.5 V - 5 12 ns
V
CC
= 6.0 V - 4 10 ns
t
W
pulse width LE HIGH; see Figure 9
V
CC
= 2.0 V 80 17 - ns
V
CC
= 4.5 V 16 6 - ns
V
CC
= 6.0 V 14 5 - ns
t
su
set-up time Dn to LE; see Figure 11
V
CC
= 2.0 V 50 14 - ns
V
CC
= 4.5 V 10 5 - ns
V
CC
= 6.0 V 9 4 - ns
t
h
hold time Dn to LE; see Figure 11
V
CC
= 2.0 V +5 8- ns
V
CC
= 4.5 V +5 3- ns
V
CC
= 6.0 V +5 2- ns
C
PD
power dissipation capacitance per latch; V
I
=GNDtoV
CC
[5]
-45-pF