Datasheet

74HC_HCT373 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 13 December 2011 13 of 26
NXP Semiconductors
74HC373; 74HCT373
Octal D-type transparent latch; 3-state
[1] t
pd
is the same as t
PLH
and t
PHL
.
[2] t
en
is the same as t
PZH
and t
PZL
.
[3] t
dis
is the same as t
PLZ
and t
PHZ
.
[4] t
t
is the same as t
THL
and t
TLH
.
[5] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
 V
CC
2
 f
i
 N+(C
L
 V
CC
2
 f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
 V
CC
2
 f
o
) = sum of outputs.
t
h
hold time Dn to LE; see Figure 11
V
CC
= 2.0 V 5 - - ns
V
CC
= 4.5 V 5 - - ns
V
CC
= 6.0 V 5 - - ns
Table 8. Dynamic characteristics 74HC373 …continued
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter Conditions Min Typ Max Unit
Table 9. Dynamic characteristics 74HCT373
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter Conditions Min Typ Max Unit
T
amb
=25C
t
pd
propagation delay Dn to Qn; see Figure 8
[1]
V
CC
= 4.5 V - 17 30 ns
V
CC
=5V; C
L
=15pF - 14 - ns
LE to Qn; see Figure 9
V
CC
= 4.5 V - 16 32 ns
V
CC
=5V; C
L
=15pF - 13 - ns
t
en
enable time OE to Qn; see Figure 10
[2]
V
CC
= 4.5 V - 19 32 ns
t
dis
disable time OE to Qn; see Figure 10
[3]
V
CC
= 4.5 V - 18 30 ns
t
t
transition time Qn; see Figure 8 and Figure 9
[4]
V
CC
= 4.5 V - 5 12 ns
t
W
pulse width LE HIGH; see Figure 9
V
CC
= 4.5 V 16 4 - ns
t
su
set-up time Dn to LE; see Figure 11
V
CC
= 4.5 V 12 6 - ns
t
h
hold time Dn to LE; see Figure 11
V
CC
= 4.5 V 4 1- ns
C
PD
power dissipation capacitance per latch;
V
I
=GNDto(V
CC
 1.5 V)
[5]
-41-pF