Datasheet

74HC3GU04 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 2 October 2013 2 of 17
NXP Semiconductors 74HC3GU04
Triple unbuffered inverter
5. Functional diagram
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 1. Logic symbol Fig 2. IEC logic symbol
mna720
1A 1Y17
2A 2Y35
3A 3Y62
7
1
1
1
5
3
mna721
1
2
6
Fig 3. Pin configuration SOT505-2 (TSSOP8) and
SOT765-1 (VSSOP8)
Fig 4. Pin configuration SOT996-2 (XSON8)
74HC3GU04
1A V
CC
3Y 1Y
2A 3A
GND 2Y
001aak022
1
2
3
4
6
5
8
7
001aak023
74HC3GU04
Transparent top view
8
7
6
5
1
2
3
4
1A
3Y
2A
GND
V
CC
1Y
3A
2Y
Table 3. Pin description
Symbol Pin Description
1A, 2A, 3A 1, 3, 6 data input
1Y, 2Y, 3Y 7, 5, 2 data output
GND 4 ground (0 V)
V
CC
8 supply voltage