Datasheet

9397 750 13812 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 03 — 12 November 2004 11 of 25
Philips Semiconductors
74HC40103
8-bit synchronous binary down counter
t
W
CP clock pulse width HIGH or
LOW
see Figure 7
V
CC
= 2.0 V 165 22 - ns
V
CC
= 4.5 V 33 8 - ns
V
CC
= 6.0 V 28 6 - ns
MR master reset pulse width
LOW
see Figure 9
V
CC
= 2.0 V 125 39 - ns
V
CC
= 4.5 V 25 14 - ns
V
CC
= 6.0 V 21 11 - ns
PL preset enable pulse width
LOW
see Figure 9
V
CC
= 2.0 V 125 33 - ns
V
CC
= 4.5 V 25 12 - ns
V
CC
= 6.0 V 21 10 - ns
t
rem
removal time MR to CP, PL to CP see Figure 10
V
CC
= 2.0 V 50 14 - ns
V
CC
= 4.5 V 10 5 - ns
V
CC
= 6.0 V 9 4 - ns
t
su
set-up time PE to CP see Figure 11
V
CC
= 2.0 V 75 22 - ns
V
CC
= 4.5 V 15 8 - ns
V
CC
= 6.0 V 13 6 - ns
set-up time
TE to CP see Figure 12
V
CC
= 2.0 V 150 44 - ns
V
CC
= 4.5 V 30 16 - ns
V
CC
= 6.0 V 26 13 - ns
set-up time Pn to CP see
Figure 11
V
CC
= 2.0 V 75 22 - ns
V
CC
= 4.5 V 15 8 - ns
V
CC
= 6.0 V 13 6 - ns
t
h
hold time PE to CP see Figure 11
V
CC
= 2.0 V 0 −14 - ns
V
CC
= 4.5 V 0 −5- ns
V
CC
= 6.0 V 0 −4- ns
hold time
TE to CP see Figure 12
V
CC
= 2.0 V 0 −30 - ns
V
CC
= 4.5 V 0 −11 - ns
V
CC
= 6.0 V 0 −9- ns
hold time Pn to CP see
Figure 11
V
CC
= 2.0 V 0 −17 - ns
V
CC
= 4.5 V 0 −6- ns
V
CC
= 6.0 V 0 −5- ns
Table 8: Dynamic characteristics
…continued
GND = 0 V; t
r
=t
f
= 6 ns; C
L
= 50 pF; see Figure 13.
Symbol Parameter Conditions Min Typ Max Unit