Datasheet

9397 750 13812 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 03 — 12 November 2004 2 of 25
Philips Semiconductors
74HC40103
8-bit synchronous binary down counter
2. Features
■ Cascadable
■ Synchronous or asynchronous preset
■ Low-power dissipation
■ Complies with JEDEC standard no. 7A
■ ESD protection:
◆ HBM EIA/JESD22-A114-B exceeds 2000 V
◆ MM EIA/JESD22-A115-A exceeds 200 V.
■ Multiple package options
■ Specified from −40 °Cto+80°C and from −40 °C to +125 °C.
3. Applications
■ Divide-by-n counters
■ Programmable timers
■ Interrupt timers
■ Cycle/program counters.
4. Quick reference data
[1] C
PD
is used to determine the dynamic power dissipation (P
D
in µW).
P
D
=C
PD
× V
CC
2
× f
i
× N+∑(C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
∑(C
L
× V
CC
2
× f
o
) = sum of outputs.
Table 1: Quick reference data
GND = 0 V; T
amb
=25 ° C; t
r
=t
f
= 6 ns.
Symbol Parameter Conditions Min Typ Max Unit
t
PHL
, t
PLH
propagation delay CP to TC C
L
= 15 pF;
V
CC
= 5 V
-30-ns
f
max
maximum clock frequency C
L
= 15 pF;
V
CC
= 5 V
- 32 - MHz
C
I
input capacitance - 3.5 - pF
C
PD
power dissipation
capacitance
V
I
= GND to V
CC
[1]
-24-pF