Datasheet

1997 Nov 25 27
Philips Semiconductors Product specification
Phase-locked-loop with VCO 74HC/HCT4046A
PLL frequency
capture range
PC1, PC2 or PC3 Loop filter component selection
(a) τ = R3 x C2 (b) amplitude characteristic (c) pole-zero diagram
A small capture range (2f
c
) is obtained if
Fig. 27 Simple loop filter for PLL without offset; R3 ≥ 500 Ω.
(a) τ1 = R3 x C2; (b) amplitude characteristic (c) pole-zero diagram
τ2 = R4 x C2;
τ3 = (R3 + R4) x C2
Fig.28 Simple loop filter for PLL with offset; R3 + R4 ≥ 500 Ω.
PLL locks on
harmonics at
centre frequency
PC1 or PC3 yes
PC2 no
noise rejection at
signal input
PC1 high
PC2 or PC3 low
AC ripple content
when PLL is
locked
PC1 f
r
=2f
i
, large ripple content at φ
DEMOUT
=90°
PC2 f
r
=f
i
, small ripple content at φ
DEMOUT
=0°
PC3 f
r
=f
i
, large ripple content at φ
DEMOUT
= 180°
SUBJECT
PHASE
COMPARATOR
DESIGN CONSIDERATIONS
2f
c
1
π
---
2 π f
L
τ⁄≈