Datasheet

74HC_HCT573_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 26 January 2015 4 of 20
NXP Semiconductors
74HC573-Q100; 74HCT573-Q100
Octal D-type transparent latch; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5. Pin configuration SO20, SSOP20 and
TSSOP20
Fig 6. Pin configuration DHVQFN20
DDD




















2
(
9
&&
'

4
'

4
'

4
'

4
'

4
'

4
'

4
'

4
*1' /(
+&4
+&74
DDD
7UDQVSDUHQWWRSYLHZ
4
'
'
4
' 4
' 4
' 4
' 4
' 4
'
*1'
4
*1'
/(
2( 9
&&
 
 
 
 
 
 
 
 




WHUPLQDO
LQGH[DUHD
+&4
+&74
Table 2. Pin description
Symbol Pin Description
OE
1 3-state output enable input (active LOW)
D[0:7] 2, 3, 4, 5, 6, 7, 8, 9 data input
GND 10 ground (0 V)
LE 11 latch enable input (active HIGH)
Q[0:7] 19, 18, 17, 16, 15, 14, 13, 12 3-state latch output
V
CC
20 supply voltage