Datasheet

74HC_HCT573_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 26 January 2015 8 of 20
NXP Semiconductors
74HC573-Q100; 74HCT573-Q100
Octal D-type transparent latch; 3-state
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 11.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
74HC573-Q100
t
pd
propagation
delay
Dn to Qn; see Figure 7
[1]
V
CC
= 2.0 V - 47 150 - 190 - 225 ns
V
CC
= 4.5 V - 17 30 - 38 - 45 ns
V
CC
=5V; C
L
=15pF - 14 - - - - - ns
V
CC
= 6.0 V - 14 26 - 33 - 38 ns
t
pd
propagation
delay
LE to Qn; see Figure 8
[1]
V
CC
= 2.0 V - 50 150 - 190 - 225 ns
V
CC
= 4.5 V - 18 30 - 38 - 45 ns
V
CC
=5V; C
L
=15pF - 15 - - - - - ns
V
CC
= 6.0 V - 14 26 - 33 - 38 ns
t
en
enable time OE to Qn; see Figure 9
[2]
V
CC
= 2.0 V - 44 140 - 175 - 210 ns
V
CC
= 4.5 V - 16 28 - 35 - 42 ns
V
CC
= 6.0 V - 13 24 - 30 - 36 ns
t
dis
disable time OE to Qn; see Figure 9
[3]
V
CC
= 2.0 V - 55 150 - 190 - 225 ns
V
CC
= 4.5 V - 20 30 - 38 - 45 ns
V
CC
= 6.0 V - 16 26 - 33 - 38 ns
t
t
transition
time
Qn; see Figure 7
[4]
V
CC
= 2.0 V - 14 60 - 75 - 90 ns
V
CC
= 4.5 V - 5 12 - 15 - 18 ns
V
CC
= 6.0 V - 4 10 - 13 - 15 ns
t
W
pulse width LE HIGH; see Figure 8
V
CC
= 2.0 V 80 14 - 100 - 120 - ns
V
CC
= 4.5 V 16 5 - 20 - 24 - ns
V
CC
= 6.0 V 14 4 - 17 - 20 - ns
t
su
set-up time Dn to LE; see Figure 10
V
CC
= 2.0 V 50 11 - 65 - 75 - ns
V
CC
= 4.5 V 10 4 - 13 - 15 - ns
V
CC
= 6.0 V 9 3 - 11 - 13 - ns
t
h
hold time Dn to LE; see Figure 10
V
CC
= 2.0 V 5 3 - 5 - 5 - ns
V
CC
= 4.5 V 5 1 - 5 - 5 - ns
V
CC
= 6.0 V 5 1 - 5 - 5 - ns
C
PD
power
dissipation
capacitance
C
L
=50pF;f=1 MHz;
V
I
=GNDtoV
CC
[5]
-26- - - - -pF