Datasheet

M54/74HC564
M54/74HC574
March 1993
HC564 INVERTING - HC574 NON INVERTING
OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT
B1R
(Plastic Package)
ORDER CODES :
M54HCXXXF1R M74HCXXXM1R
M74HCXXXB1R M74HCXXXC1R
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
PIN CONNECTION (top view)
.HIGH SPEED
f
MAX
= 62 MHz (TYP.) AT V
CC
=5V
.LOW POWER DISSIPATION
I
CC
=4µA (MAX.) AT T
A
=25°C
.HIGH NOISE IMMUNITY
V
NIH
=V
NIL
= 28% V
CC
(MIN)
.OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
.SYMMETRICAL OUTPUT IMPEDANCE
I
OL
= I
OH
= 6 mA (MIN.)
.BALANCED PROPAGATION DELAYS
t
PLH
=t
PHL
.WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO 6 V
.PIN AND FUNCTION COMPATIBLE
WITH 54/74LS564/574
DESCRIPTION
The M54/74HC564 and M54HC574 are high speed
CMOS OCTAL D-TYPE FLIP FLOPWITH3-STATE
OUTPUTS fabricated with in silicon gate C
2
MOS
technology. They have the same high speed per-
formance of LSTTL combined with true CMOS low
power comsuption. These8-bit D-type flip-flops are
controlled by a clockinput(CK) and anouput enable
input (OE).On thepositive transition of theclock, the
Q outputs willbesetto thelogic statethatweresetup
at the D inputs (HC574) or their complements
(HC564).
While the OE input is low, the eight outputs will be
in a normal logic state (high or low logic level), and
while high level, the outputs will be in a high imped-
ance state. The output control does notaffect the in-
ternal operation of flip-flops. That is, theold data can
be retained or the new data can be entered even
while the outputs are off. The application engineer
has a choice of combination of inverting and non-in-
verting outputs. The 3-state output configuration
and the wide choice of outline make bus-organized
systemssimple.Allinputs are equipped withprotec-
tion circuits against static discharge and transient
excess voltage.
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