Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Gate AND gate 74HCT TSSOP 14

1. General description

The 74HC08; 74HCT08 is a quad 2-input AND gate. Inputs include clamp diodes. This

enables the use of current limiting resistors to interface inputs to voltages in excess of

2. Features and benefits

 Complies with JEDEC standard JESD7A

 Complies with JEDEC standard JESD8-1A

 Input levels:

 For 74HC08: CMOS level

 For 74HCT08: TTL level

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V

 Multiple package options

 Specified from 40 C to +85 C and from 40 C to +125 C

3. Ordering information

74HC08; 74HCT08

Quad 2-input AND gate

Rev. 4 — 6 September 2012 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74HC08N 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1

74HCT08N

74HC08D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width

3.9 mm

SOT108-1

74HCT08D

74HC08DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body

width 5.3 mm

SOT337-1

74HCT08DB

74HC08PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

74HCT08PW

74HC08BQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very

thin quad flat package; no leads; 14 terminals;

body 2.5  3  0.85 mm

SOT762-1

74HCT08BQ

Summary of content (16 pages)

PAGE 1
74HC08; 74HCT08 Quad 2-input AND gate Rev. 4 — 6 September 2012 Product data sheet 1. General description The 74HC08; 74HCT08 is a quad 2-input AND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2.
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74HC08; 74HCT08 NXP Semiconductors Quad 2-input AND gate 4. Functional diagram 1 & 3 & 6 & 8 2 4 1 1A 2 1B 4 2A 5 2B 9 3A 10 3B 12 4A 13 4B 1Y 3 5 2Y 6 9 10 3Y 8 4Y 11 A 12 & Y 11 13 B mna222 Fig 1. mna221 mna223 Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 5. Pinning information 5.
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74HC08; 74HCT08 NXP Semiconductors Quad 2-input AND gate 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A to 4A 1, 4, 9, 12 data input 1B to 4B 2, 5, 10,13 data input 1Y to 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) VCC 14 supply voltage 6. Functional description Table 3. Function table[1] Input Output nA nB L L L L H L H L L H H H [1] nY H = HIGH voltage level; L = LOW voltage level; X = don’t care. 7. Limiting values Table 4.
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74HC08; 74HCT08 NXP Semiconductors Quad 2-input AND gate 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC08 Min 74HCT08 Typ Max Min Unit Typ Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.
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74HC08; 74HCT08 NXP Semiconductors Quad 2-input AND gate Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions Min CI input capacitance Typ 40 C to +85 C 40 C to +125 C Unit Max Min Max Min Max - 3.5 - - - - - pF 74HCT08 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.
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74HC08; 74HCT08 NXP Semiconductors Quad 2-input AND gate Table 7. Dynamic characteristics GND = 0 V; CL = 50 pF; for load circuit see Figure 7. Symbol Parameter CPD 25 C Conditions power dissipation capacitance 40 C to +125 C Unit Min Typ Max Max (85 C) Max (125 C) - 10 - - - VCC = 4.5 V - 14 24 30 36 ns VCC = 5.
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4HC08; 74HCT08 NXP Semiconductors Quad 2-input AND gate VI negative pulse tW 90 % VM VM 10 % GND tr tf tr tf VI 90 % positive pulse GND VM VM 10 % tW VCC G VI VO DUT RT CL 001aah768 Test data is given in Table 9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. Fig 7. Table 9.
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74HC08; 74HCT08 NXP Semiconductors Quad 2-input AND gate 12. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.
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74HC08; 74HCT08 NXP Semiconductors Quad 2-input AND gate SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.
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74HC08; 74HCT08 NXP Semiconductors Quad 2-input AND gate SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.
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74HC08; 74HCT08 NXP Semiconductors Quad 2-input AND gate TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.
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74HC08; 74HCT08 NXP Semiconductors Quad 2-input AND gate DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.1 2.
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74HC08; 74HCT08 NXP Semiconductors Quad 2-input AND gate 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT08 v.
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74HC08; 74HCT08 NXP Semiconductors Quad 2-input AND gate 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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74HC08; 74HCT08 NXP Semiconductors Quad 2-input AND gate Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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74HC08; 74HCT08 NXP Semiconductors Quad 2-input AND gate 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . .