Datasheet

74HC_HCT166 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 11 September 2013 11 of 21
NXP Semiconductors
74HC166; 74HCT166
8-bit parallel-in/serial out shift register
[1] t
pd
is the same as t
PHL
and t
PLH
.
[2] t
t
is the same as t
THL
and t
TLH
.
[3] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
= C
PD
 V
CC
2
 f
i
+ (C
L
 V
CC
2
 f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
 (C
L
 V
CC
2
 f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V.
11. Waveforms
f
max
maximum
frequency
CP input; see Figure 7
V
CC
= 4.5 V 25 45 - 20 - 17 - MHz
V
CC
= 5.0 V; C
L
=15pF - 50 - - - - - MHz
C
PD
power
dissipation
capacitance
per package;
V
I
=GNDtoV
CC
[3]
-41- - - - - pF
Table 7. Dynamic characteristics
…continued
GND (ground = 0 V); t
r
= t
f
= 6 ns: C
L
= 50 pF unless otherwise specified; for test circuit, see Figure 10
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 7. Clock (CP) to output (Q7) propagation delays, pulse width, output transition times and maximum
frequency
aaa-008821
CP input
Q7 output
90 %
10 % 10 %
90 %
GND
V
M
V
I
V
OH
V
OL
V
M
t
W
t
PHL
t
PLH
t
TLH
t
THL
1/f
max