Datasheet

74HC_HCT166 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 11 September 2013 12 of 21
NXP Semiconductors
74HC166; 74HCT166
8-bit parallel-in/serial out shift register
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 8. Master reset (MR) pulse width, MR to output (Q7) propagation delay and MR to clock (CP) recovery time.
aaa-008822
Q7 output
V
M
t
PHL
V
M
MR input
V
M
t
W
V
I
GND
t
rec
V
I
V
OH
V
OL
GND
CP input
The shaded areas indicate when the input is permitted to change for predictable output performance
Measurement points are given in Table 8
.
(1) CE
may change only from HIGH-to-LOW while CP is LOW
Fig 9. Set-up and hold times
aaa-008823
V
M
V
I
GND
V
I
GND
V
I
GND
V
I
GND
V
I
GND
V
M
see note (1)
CE input
PE input
Dn input
V
M
V
M
DS input
stable
V
M
CP input
condition: MR = HIGH
stable
t
h
t
h
t
h
t
su
t
su
t
su
t
h
t
h
t
su
t
h
t
su
t
h
t
W
t
su
t
su