Datasheet
74HC_HCT175 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 8 April 2014 10 of 19
NXP Semiconductors
74HC175; 74HCT175
Quad D-type flip-flop with reset; positive-edge trigger
Measurement points are given in Table 8.
Fig 9. Data set-up and hold times for data input
DDD
9
0
&3LQSXW
'QLQSXW
4QRXWSXW
4QRXWSXW
9
0
9
0
9
0
W
VX
W
VX
W
K
W
K
*1'
9
,
*1'
9
,
9
2/
9
2+
9
2/
9
2+
Measurement points are given in Table 8.
Fig 10. Master reset to output propagation delays, master reset pulse width and master reset to clock recovery
time
4QRXWSXW
DDD
9
0
W
:
W
UHP
9
0
9
0
9
0
W
3+/
&3LQSXW
05LQSXW
4QRXWSXW
W
3/+
*1'
9
,
*1'
9
,
9
2/
9
2+
9
2/
9
2+
Table 8. Measurement points
Type Input Output
V
I
V
M
V
M
74HC175 V
CC
0.5V
CC
0.5V
CC
74HCT175 3 V 1.3 V 1.3 V