Datasheet
74HC_HCT175 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 8 April 2014 3 of 19
NXP Semiconductors
74HC175; 74HCT175
Quad D-type flip-flop with reset; positive-edge trigger
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 4. Pin configuration DIP16 Fig 5. Pin configuration SO16 Fig 6. Pin configuration SSOP16
and TSSOP16
DDD
9
&&
4
4
'
'
4
4
&3
+&
+&7
0
5
4
4
'
'
4
4
*1'
DDD
0
5
9
&&
4
4
4
4
'
'
'
'
4
4
4
4
*1' &3
+&
+&7
DDD
9
&&
4
4
'
'
4
4
&3
4
4
'
'
4
4
*1'
0
5
+&
+&7
Table 2. Pin description
Symbol Pin Description
MR
1 asynchronous master reset input (active LOW)
Q0 to Q3 2, 7, 10, 15 flip-flop output
Q0
to Q3 3, 6, 11, 14 complementary flip-flop output
D0 to D3 4, 5, 12, 13 data input
GND 8 ground (0 V)
CP 9 clock input (LOW-to-HIGH edge-triggered)
V
CC
16 positive supply voltage