Datasheet

74HC_HCT175 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 8 April 2014 8 of 19
NXP Semiconductors
74HC175; 74HCT175
Quad D-type flip-flop with reset; positive-edge trigger
t
h
hold time Dn to CP; see Figure 8
V
CC
= 2.0 V 25 2 - 30 - 40 - ns
V
CC
= 4.5 V 5 0 - 6 - 8 - ns
V
CC
= 6.0 V 4 0 - 5 - 7 - ns
f
max
maximum
frequency
CP input; see Figure 8
V
CC
= 2.0 V 6 25 - 4.8 - 4 - MHz
V
CC
= 4.5 V 30 75 - 24 - 20 - MHz
V
CC
=5V; C
L
=15pF - 83 - - - - - MHz
V
CC
= 6.0 V 35 89 - 28 - 24 - MHz
C
PD
power
dissipation
capacitance
per package;
V
I
=GNDtoV
CC
[3]
-32---- - pF
74HCT175
t
pd
propagation
delay
CP to Qn, Qn;
see Figure 8
[1]
V
CC
= 4.5 V - 19 33 - 41 - 50 ns
V
CC
=5V; C
L
=15pF-16---- - ns
t
PHL
HIGH to LOW
propagation
delay
MR to Qn; see Figure 10
V
CC
= 4.5 V - 22 38 - 48 - 57 ns
V
CC
=5V; C
L
=15pF-19---- - ns
MR
to Qn; see Figure 10
V
CC
= 4.5 V - 19 35 - 44 - 53 ns
V
CC
=5V; C
L
=15pF-16---- - ns
t
t
transition time Qn output; see Figure 8
[2]
V
CC
= 4.5 V - 7 15 - 19 - 22 ns
t
W
pulse width CP input; see Figure 8
V
CC
= 4.5 V 20 12 - 25 - 30 - ns
MR
input LOW;
see Figure 10
V
CC
= 4.5 V 20 11 - 25 - 30 - ns
t
rec
recovery time MR to CP; see Figure 10
V
CC
= 4.5 V 5 10 - 5 - 5 - ns
t
su
set-up time Dn to CP; see Figure 8
V
CC
= 4.5 V 16 5 - 20 - 24 - ns
t
h
hold time Dn to CP; see Figure 8
V
CC
= 4.5 V 5 0 - 5 - 5 - ns
Table 7. Dynamic characteristics
…continued
GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit, see Figure 11
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max