Datasheet

74HC_HCT175 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 8 April 2014 9 of 19
NXP Semiconductors
74HC175; 74HCT175
Quad D-type flip-flop with reset; positive-edge trigger
[1] t
pd
is the same as t
PHL
and t
PLH
.
[2] t
t
is the same as t
THL
and t
TLH
.
[3] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
= C
PD
 V
CC
2
 f
i
+ (C
L
 V
CC
2
 f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
 (C
L
 V
CC
2
 f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V.
11. Waveforms
f
max
maximum
frequency
CP input; see Figure 8
V
CC
= 4.5 V 25 49 - 20 - 17 - MHz
V
CC
=5V; C
L
=15pF - 54 - - - - - MHz
C
PD
power
dissipation
capacitance
per package;
V
I
=GNDtoV
CC
 1.5 V
[3]
-34---- - pF
Table 7. Dynamic characteristics
…continued
GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit, see Figure 11
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
Measurement points are given in Table 8.
Fig 8. Input to output propagation delay, output transition time, clock input pulse width and maximum
frequency
DDD
W
:
W
3+/
W
3+/
W
7/+
W
7+/
W
7/+
9
0
9
0
I
PD[
W
3/+
W
7+/
W
3/+
9
0
&
3LQSXW
4QRXWSXW
4QRXWSXW
*1'
9
,
9
2/
9
2+
9
2/
9
2+