Datasheet

74HC_HCT193 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 24 June 2013 17 of 30
NXP Semiconductors
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
[1] t
pd
is the same as t
PHL
and t
PLH
.
[2] C
PD
is used to determine the dynamic power dissipation (P
D
in W):
P
D
=C
PD
 V
CC
2
 f
i
 N+(C
L
 V
CC
2
 f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
 V
CC
2
 f
o
) = sum of outputs.
t
rec
recovery time PL to CPU, CPD;
see Figure 11
V
CC
=4.5V 10 2 - 13 - 15 - ns
MR to CPU, CPD;
see Figure 12
V
CC
=4.5V 10 0 - 13 - 15 - ns
t
su
set-up time Dn to PL; see
Figure 13; note:
CPU = CPD =
HIGH
V
CC
=4.5V 16 8 - 20 - 24 - ns
t
h
hold time Dn to PL; see
Figure 13
V
CC
=4.5V 0 6- 0 - 0 -ns
CPU to CPD,
CPD to CPU; see
Figure 15
V
CC
=4.5V 16 7 - 20 - 24 - ns
f
max
maximum
frequency
CPU, CPD; see
Figure 9
V
CC
=4.5V 20 43 - 16 - 13 - MHz
C
PD
power
dissipation
capacitance
V
I
= GND to V
CC

1.5 V; V
CC
=5V;
f
i
=1MHz
[2]
-26- - - - -pF
Table 9. Dynamic characteristics type 74HCT193
…continued
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max