Datasheet

74HC_HCT193 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 24 June 2013 18 of 30
NXP Semiconductors
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
11. Waveforms
Measurement points are given in Tabl e 1 0.
t
PLH
and t
PHL
are the same as t
pd
.
Logic levels V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 9. The clock (CPU, CPD) to output (Qn) propagation delays, the clock pulse width, and the maximum clock
pulse frequency
001aag413
CPU, CPD
input
V
I
GND
V
OH
V
OL
Qn output
t
PHL
t
PLH
t
W
V
M
V
M
1/f
max
Measurement points are given in Tabl e 1 0.
t
PLH
and t
PHL
are the same as t
pd
.
Logic levels V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 10. The clock (CPU, CPD) to terminal count output (TCU,TCD) propagation delays
001aag414
CPU, CPD
input
TCU, TCD
output
t
PHL
V
I
GND
V
OH
V
OL
t
PLH
V
M
V
M