Datasheet

74HC_HCT193 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 24 June 2013 20 of 30
NXP Semiconductors
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Tabl e 1 0
.
Logic levels V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 13. The data input (Dn) to parallel load input (PL) set-up and hold times
001aag417
Dn input
Qn output
V
OL
V
OH
GND
V
I
GND
V
I
PL input
V
M
t
su
t
h
V
M
t
su
t
h
Measurement points are given in Tabl e 1 0.
t
PLH
and t
PHL
are the same as t
pd
.
Logic levels V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 14. The data input (Dn), parallel load input (PL) and the master reset input (MR) to the terminal count outputs
(TCU,TCD) propagation delays
001aag418
PL, MR, Dn
input
TCU, TCD
output
t
PLH
t
PHL
V
M
V
M
V
OL
V
OH
GND
V
I
Measurement points are given in Tabl e 1 0.
Fig 15. The CPU to CPD or CPD to CPU hold times
001aag419
CPD or CPU
input
CPU or CPD
input
V
I
GND
V
I
GND
V
M
V
M
t
h