Datasheet
74HC_HCT193 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 24 June 2013 5 of 30
NXP Semiconductors
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
5. Pinning information
5.1 Pinning
5.2 Pin description
[1] LOW-to-HIGH, edge triggered.
Fig 5. Pin configuration SO16 Fig 6. Pin configuration TSSOP16
and SSOP16
Fig 7. Pin configuration DIP16
D1
V
CC
Q1 D0
Q0 MR
CPD TCD
CPU TCU
Q2 PL
Q3 D2
GND D3
001aag406
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
74HC193
74HCT193
74HC193
74HCT193
D1 V
CC
Q1 D0
Q0 MR
CPD TCD
CPU TCU
Q2 PL
Q3 D2
GND D3
001aag407
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
74HC193
74HCT193
D1 V
CC
Q1 D0
Q0 MR
CPD TCD
CPU TCU
Q2 PL
Q3 D2
GND D3
001aaf408
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
Table 2. Pin description
Symbol Pin Description
D0 15 data input 0
D1 1 data input 1
D2 10 data input 2
D3 9 data input 3
Q0 3 flip-flop output 0
Q1 2 flip-flop output 1
Q2 6 flip-flop output 2
Q3 7 flip-flop output 3
CPD 4 count down clock input
[1]
CPU 5 count up clock input
[1]
GND 8 ground (0 V)
PL
11 asynchronous parallel load input (active LOW)
TCU
12 terminal count up (carry) output (active LOW)
TCD
13 terminal count down (borrow) output (active LOW)
MR 14 asynchronous master reset input (active HIGH)
V
CC
16 supply voltage