Datasheet

Product data sheet Rev. 4 — 24 June 2013 7 of 30

NXP Semiconductors

74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

(1) Clear overrides load, data and count inputs.

(2) When counting up, the count down clock input (CPD) must be HIGH, when counting down the count up clock input

(CPU) must be HIGH.

Sequence

Clear (reset outputs to zero);

load (preset) to binary thirteen;

count up to fourteen, fifteen, terminal count up, zero, one and two;

count down to one, zero, terminal count down, fifteen, fourteen and thirteen.

Fig 8. Typical clear, load and count sequence

001aag411

COUNT UP COUNT DOWN

013

CLEAR PRESET

1 0 15 14 1314 15 0 1 2

(1)

CPU

(2)

CPD

(2)

TCU

TCD