Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Gate AND gate 74HCT TSSOP 5

1. General description

74HC1G08 and 74HCT1G08 are high-speed, Si-gate CMOS devices. They provide a

2-input AND function.

The HC device has CMOS input switching levels and supply voltage range 2 V to 6 V.

The HCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V.

The standard output currents are half those of the 74HC08 and 74HCT08.

2. Features

n Symmetrical output impedance

n High noise immunity

n Low power dissipation

n Balanced propagation delays

n SOT353-1 and SOT753 package options

3. Ordering information

4. Marking

74HC1G08; 74HCT1G08

2-input AND gate

Rev. 04 — 17 July 2007 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74HC1G08GW −40 °C to +125 °C TSSOP5 plastic thin shrink small outline package; 5 leads;

body width 1.25 mm

SOT353-1

74HCT1G08GW

74HC1G08GV −40 °C to +125 °C SC-74A plastic surface-mounted package; 5 leads SOT753

74HCT1G08GV

Table 2. Marking codes

Type number Marking

74HC1G08GW HE

74HCT1G08GW TE

74HC1G08GV H08

74HCT1G08GV T08

Summary of content (11 pages)

PAGE 1
74HC1G08; 74HCT1G08 2-input AND gate Rev. 04 — 17 July 2007 Product data sheet 1. General description 74HC1G08 and 74HCT1G08 are high-speed, Si-gate CMOS devices. They provide a 2-input AND function. The HC device has CMOS input switching levels and supply voltage range 2 V to 6 V. The HCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V. The standard output currents are half those of the 74HC08 and 74HCT08. 2.
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74HC1G08; 74HCT1G08 NXP Semiconductors 2-input AND gate 5. Functional diagram 1 B 2 A 1 Y 4 & 4 2 mna113 mna114 Fig 1. Logic symbol Fig 2. IEC logic symbol B Y A mna115 Fig 3. Logic diagram 6. Pinning information 6.1 Pinning 74HC1G08 74HCT1G08 B 1 A 2 GND 3 5 VCC 4 Y 001aaf102 Fig 4. Pin configuration 6.2 Pin description Table 3.
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74HC1G08; 74HCT1G08 NXP Semiconductors 2-input AND gate 7. Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level Input Output A B Y L L L L H L H L L H H H 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). [1] Symbol Parameter VCC supply voltage IIK input clamping current IOK Min Max Unit −0.5 +7.0 V VI < −0.5 V or VI > VCC + 0.
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74HC1G08; 74HCT1G08 NXP Semiconductors 2-input AND gate 10. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). All typical values are measured at Tamb = 25 °C. Symbol Parameter −40 °C to +85 °C Conditions −40 °C to +125 °C Unit Min Typ Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.
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74HC1G08; 74HCT1G08 NXP Semiconductors 2-input AND gate Table 7. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). All typical values are measured at Tamb = 25 °C. Symbol Parameter −40 °C to +85 °C Conditions −40 °C to +125 °C Min Typ Max Min Max Unit ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 10 - 20 µA ∆ICC additional supply current per input; VCC = 4.5 V to 5.5 V; VI = VCC − 2.
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74HC1G08; 74HCT1G08 NXP Semiconductors 2-input AND gate 12. Waveforms A, B input VM VCC tPHL Y output tPLH PULSE GENERATOR VM VI VO DUT CL RT mna101 mna116 For 74HC1G08: VM = 0.5 × VCC; VI = GND to VCC For 74HCT1G08: VM = 1.3 V; VI = GND to 3.0 V Test data is given in Table 8. Definitions for test circuit: CL = Load capacitance including jig and probe capacitance RT = Termination resistance should be equal to the output impedance Zo of the pulse generator Fig 5.
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4HC1G08; 74HCT1G08 NXP Semiconductors 2-input AND gate 13. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm E D SOT353-1 A X c y HE v M A Z 5 4 A2 A (A3) A1 θ 1 Lp 3 L e w M bp detail X e1 0 1.5 3 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e e1 HE L Lp v w y Z(1) θ mm 1.1 0.1 0 1.0 0.8 0.15 0.30 0.15 0.25 0.08 2.25 1.85 1.35 1.15 0.65 1.3 2.25 2.0 0.
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74HC1G08; 74HCT1G08 NXP Semiconductors 2-input AND gate Plastic surface-mounted package; 5 leads SOT753 D E B y A X HE 5 v M A 4 Q A A1 c 1 2 3 Lp detail X bp e w M B 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp c D E e HE Lp Q v w y mm 1.1 0.9 0.100 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.
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74HC1G08; 74HCT1G08 NXP Semiconductors 2-input AND gate 14. Abbreviations Table 9. Abbreviations Acronym Description DUT Device Under Test TTL Transistor-Transistor Logic 15. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT1G08_4 20070717 Product data sheet - 74HC_HCT1G08_3 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors.
PAGE 10
74HC1G08; 74HCT1G08 NXP Semiconductors 2-input AND gate 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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NXP Semiconductors 74HC1G08; 74HCT1G08 2-input AND gate 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . .