Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Gate and inverter NAND gate 74HCT TSSOP 14

1. General description

The 74HC30; 74HCT30 is an 8-input NAND gate. Inputs include clamp diodes. This

enables the use of current limiting resistors to interface inputs to voltages in excess of

2. Features and benefits

 Complies with JEDEC standard JESD7A

 Input levels:

 For 74HC30: CMOS level

 For 74HCT30: TTL level

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V

 Multiple package options

 Specified from 40 C to +85 C and from 40 C to +125 C

3. Ordering information

74HC30; 74HCT30

8-input NAND gate

Rev. 6 — 27 December 2012 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74HC30N 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1

74HCT30N

74HC30D 40 C to +125 C SO14 plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

74HCT30D

74HC30DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body

width 5.3 mm

SOT337-1

74HCT30DB

74HC30PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

74HCT30PW

Summary of content (16 pages)

PAGE 1
74HC30; 74HCT30 8-input NAND gate Rev. 6 — 27 December 2012 Product data sheet 1. General description The 74HC30; 74HCT30 is an 8-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2.
PAGE 2
74HC30; 74HCT30 NXP Semiconductors 8-input NAND gate 4. Functional diagram 1 A 1 2 B 2 3 C 4 D 5 E 6 F 6 11 G 11 12 H 12 3 4 8 Y 8 5 mna489 mna488 Fig 1. & Logic symbol Fig 2. IEC logic symbol A B C D Y E mna490 F G H Fig 3. Logic diagram 74HC_HCT30 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 27 December 2012 © NXP B.V. 2012. All rights reserved.
PAGE 3
74HC30; 74HCT30 NXP Semiconductors 8-input NAND gate 5. Pinning information 5.1 Pinning 74HC30 74HCT30 A 1 14 VCC B 2 13 n.c. C 3 12 H D 4 11 G E 5 10 n.c. F 6 9 n.c. GND 7 8 Y 001aal790 Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 5.2 Pin description Table 2. Pin description Symbol Pin Description A 1 data input B 2 data input C 3 data input D 4 data input E 5 data input F 6 data input GND 7 ground (0 V) Y 8 data output n.c.
PAGE 4
74HC30; 74HCT30 NXP Semiconductors 8-input NAND gate 6. Functional description Table 3. Function table[1] Input Output A B C D E F G H Y L X X X X X X X H X L X X X X X X H X X L X X X X X H X X X L X X X X H X X X X L X X X H X X X X X L X X H X X X X X X L X H X X X X X X X L H H H H H H H H H L [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. 7. Limiting values Table 4.
PAGE 5
74HC30; 74HCT30 NXP Semiconductors 8-input NAND gate 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC30 Min Typ 74HCT30 Max Min Typ Unit Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.
PAGE 6
74HC30; 74HCT30 NXP Semiconductors 8-input NAND gate Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter CI 25 C Conditions input capacitance 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max - 3.5 - - - - - pF 74HCT30 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.
PAGE 7
4HC30; 74HCT30 NXP Semiconductors 8-input NAND gate Table 7. Dynamic characteristics …continued GND = 0 V; CL = 50 pF; for load circuit see Figure 6. Symbol Parameter CPD 25 C Conditions power dissipation capacitance [3] per package; VI = GND to VCC 40 C to +125 C Unit Min Typ Max Max (85 C) Max (125 C) - 15 - - - pF - 16 28 35 42 ns 74HCT30 [1] propagation delay A, B, C, D, E, F, G, H to Y; see Figure 5 tpd VCC = 4.5 V VCC = 5.
PAGE 8
74HC30; 74HCT30 NXP Semiconductors 8-input NAND gate VI negative pulse tW 90 % VM VM 10 % GND tr tf tr tf VI 90 % positive pulse GND VM VM 10 % tW VCC G VI VO DUT RT CL 001aah768 Test data is given in Table 9. Definitions for test circuit: RT = termination resistance should be equal to the output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. Fig 6. Table 9.
PAGE 9
74HC30; 74HCT30 NXP Semiconductors 8-input NAND gate 12. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.
PAGE 10
74HC30; 74HCT30 NXP Semiconductors 8-input NAND gate SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.
PAGE 11
74HC30; 74HCT30 NXP Semiconductors 8-input NAND gate SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.
PAGE 12
74HC30; 74HCT30 NXP Semiconductors 8-input NAND gate TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.
PAGE 13
74HC30; 74HCT30 NXP Semiconductors 8-input NAND gate 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT30 v.
PAGE 14
74HC30; 74HCT30 NXP Semiconductors 8-input NAND gate 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
PAGE 15
74HC30; 74HCT30 NXP Semiconductors 8-input NAND gate Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
PAGE 16
74HC30; 74HCT30 NXP Semiconductors 8-input NAND gate 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . .