Datasheet

74HC_HCT573 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 6 — 26 January 2015 5 of 21
NXP Semiconductors
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
6. Functional description
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.
7. Limiting values
[1] For DIP20 package: P
tot
derates linearly with 12 mW/K above 70 C.
[2] For SO20: P
tot
derates linearly with 8 mW/K above 70 C.
For SSOP20 and TSSOP20 packages: P
tot
derates linearly with 5.5 mW/K above 60 C.
For DHVQFN20 package: P
tot
derates linearly with 4.5 mW/K above 60 C.
Table 3. Function table
[1]
Operating mode Control Input Internal
latches
Output
OE LE Dn Qn
Enable and read register (transparent
mode)
LHLLL
HHH
Latch and read register L L l L L
hHH
Latch register and disable outputs H L l L Z
hHZ
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +7 V
I
IK
input clamping current V
I
< 0.5 V or V
I
>V
CC
+0.5 V - 20 mA
I
OK
output clamping current V
O
< 0.5 V or V
O
>V
CC
+0.5V - 20 mA
I
O
output current V
O
= 0.5 V to (V
CC
+0.5V) - 35 mA
I
CC
supply current - +70 mA
I
GND
ground current - 70 mA
T
stg
storage temperature 65 +150 C
P
tot
total power dissipation DIP20 package
[1]
- 750 mW
SO20, SSOP20, TSSOP20 and
DHVQFN20 packages
[2]
- 500 mW