Datasheet

74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 7 — 26 January 2015 11 of 24
NXP Semiconductors
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
[1] Typical values are measured at nominal supply voltage.
[2] t
pd
is the same as t
PHL
and t
PLH
.
[3] t
pd
is the same as t
PHL
only.
[4] t
en
is the same as t
PZL
and t
PZH
.
[5] t
dis
is the same as t
PLZ
and t
PHZ
.
[6] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
 V
CC
2
 f
i
+ (C
L
 V
CC
2
 f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
(C
L
 V
CC
2
 f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V.
[7] All 9 outputs switching.
74HCT595; V
CC
= 4.5 V to 5.5 V
t
pd
propagation
delay
SHCP to Q7S; see Figure 9
[2]
-2542 - 53 - 63ns
STCP to Qn; see Figure 10
[2]
-2440 - 50 - 60ns
MR
to Q7S; see Figure 12
[3]
-2340 - 50 - 60ns
t
en
enable time OE to Qn; see Figure 13
[4]
-2135 - 44 - 53ns
t
dis
disable time OE to Qn; see Figure 13
[5]
-1830 - 38 - 45ns
t
W
pulse width SHCP HIGH or LOW;
see Figure 9
16 6 - 20 - 24 - ns
STCP HIGH or LOW;
see Figure 10
16 5 - 20 - 24 - ns
MR
LOW; see Figure 12 20 8 - 25 - 30 - ns
t
su
set-up time DS to SHCP; see Figure 10 16 5 - 20 - 24 - ns
SHCP to STCP;
see Figure 11
16 8 - 20 - 24 - ns
t
h
hold time DS to SHCP; see Figure 11 3 2- 3 - 3 - ns
t
rec
recovery
time
MR to SHCP; see Figure 12 10 7- 13 - 15 - ns
f
max
maximum
frequency
SHCP and STCP;
see Figure 9
and 10
30 52 - 24 - 20 - MHz
C
PD
power
dissipation
capacitance
f
i
= 1 MHz;
V
I
=GNDtoV
CC
 1.5 V
[6]
[7]
- 130 - - - - - pF
Table 7. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 14.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max Min Max