Datasheet

74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 7 — 26 January 2015 6 of 24
NXP Semiconductors
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
8. Limiting values
[1] For DIP16 package: P
tot
derates linearly with 12 mW/K above 70 C.
[2] For SO16 package: P
tot
derates linearly with 8 mW/K above 70 C.
[3] For SSOP16 and TSSOP16 packages: P
tot
derates linearly with 5.5 mW/K above 60 C.
[4] For DHVQFN16 package: P
tot
derates linearly with 4.5 mW/K above 60 C.
Fig 8. Timing diagram
6+&3
'6
67&3
05
2(
4
4
4
4
46
=VWDWH
=VWDWH
=VWDWH
=VWDWH
PQD
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +7 V
I
IK
input clamping current V
I
< 0.5 V or V
I
>V
CC
+ 0.5 V - 20 mA
I
OK
output clamping current V
O
< 0.5 V or V
O
> V
CC
+ 0.5 V - 20 mA
I
O
output current V
O
= 0.5 V to (V
CC
+0.5V)
pin Q7S - 25 mA
pins Qn - 35 mA
I
CC
supply current - 70 mA
I
GND
ground current 70 - mA
T
stg
storage temperature 65 +150 C
P
tot
total power dissipation DIP16 package
[1]
- 750 mW
SO16 package
[2]
- 500 mW
SSOP16 package
[3]
- 500 mW
TSSOP16 package
[3]
- 500 mW
DHVQFN16 package
[4]
- 500 mW