Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLinear ICs74HCT9046APW,118

1. General description

The 74HCT9046A is a high-speed Si-gate CMOS device. It is speciﬁed in compliance with

JEDEC standard no 7A.

2. Features

n Operation power supply voltage range from 4.5 V to 5.5 V

n Low power consumption

n Inhibit control for ON/OFF keying and for low standby power consumption

n center frequency up to 17 MHz (typical) at V

= 5.5 V

n Choice of two phase comparators:

u PC1: EXCLUSIVE-OR

u PC2: Edge-triggered JK ﬂip-ﬂop

n No dead zone of PC2

n Charge pump output on PC2, whose current is set by an external resistor R

bias

n center frequency tolerance ±10 %

n Excellent Voltage Controlled Oscillator (VCO) linearity

n Low frequency drift with supply voltage and temperature variations

n On-chip band gap reference

n Glitch free operation of VCO, even at very low frequencies

n Zero voltage offset due to operational ampliﬁer buffering

n ESD protection:

u HBM JESD22-A114F exceeds 2000 V

u MM JESD22-A115-A exceeds 200 V

74HCT9046A

PLL with band gap controlled VCO

Rev. 06 — 15 September 2009 Product data sheet

Summary of content (43 pages)

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74HCT9046A PLL with band gap controlled VCO Rev. 06 — 15 September 2009 Product data sheet 1. General description The 74HCT9046A is a high-speed Si-gate CMOS device. It is specified in compliance with JEDEC standard no 7A. 2. Features n n n n n n n n n n n n n n Operation power supply voltage range from 4.5 V to 5.5 V Low power consumption Inhibit control for ON/OFF keying and for low standby power consumption center frequency up to 17 MHz (typical) at VCC = 5.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO 3. Applications n FM modulation and demodulation where a small center frequency tolerance is essential n Frequency synthesis and multiplication where a low jitter is required (e.g. video picture-in-picture) n Frequency discrimination n Tone decoding n Data synchronization and conditioning n Voltage-to-frequency conversion n Motor-speed control 4. Ordering information Table 1.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO 5. Block diagram fout C1 fin C1A 6 VCC C1B VCO_OUT COMP_IN SIG_IN 7 4 3 14 16 9046A R2 12 R2 PHASE COMPARATOR 1 VCO R1 11 PHASE COMPARATOR 2 R1 PC1_OUT/ 2 PCP_OUT 13 PC2_OUT 15 RB R4 Rbias 5 10 9 DEM_OUT VCO_IN INH 8 1 GND GND C2 Rs Fig 1. R3 mbd040 Block diagram 6.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO 7. Pinning information 7.1 Pinning 74HCT9046A 1 16 VCC 2 15 RB COMP_IN 3 14 SIG_IN VCO_OUT 4 13 PC2_OUT INH 5 12 R2 C1A 6 11 R1 C1B 7 10 DEM_OUT GND 8 GND PC1_OUT/ PCP_OUT 9 VCO_IN 001aae500 Fig 5. Pin configuration 7.2 Pin description Table 2.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO 8. Functional description The 74HCT9046A is a phase-locked-loop circuit that comprises a linear VCO and two different phase comparators (PC1 and PC2) with a common signal input amplifier and a common comparator input, see Figure 1. The signal input can be directly coupled to large voltage signals (CMOS level), or indirectly coupled (with a series capacitor) to small voltage signals.
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4HCT9046A NXP Semiconductors PLL with band gap controlled VCO • The inhibit function differs. For the 74HCT4046A a HIGH-level at the inhibit input (pin INH) disables the VCO and demodulator, while a LOW-level turns both on. For the 74HCT9046A a HIGH-level on the inhibit input disables the whole circuit to minimize standby power consumption. 8.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO waveforms for the PC1 loop locked at f0 are shown in Figure 7. This figure also shows the actual waveforms across the VCO capacitor at pins C1A and C1B (VC1A and VC1B) to show the relation between these ramps and the VCO_OUT voltage. The frequency capture range (2f0) is defined as the frequency range of input signals on which the PLL will lock if it was initially out-of-lock.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO SIGN_IN COMP_IN VCO_OUT PC1_OUT VCC VCO_IN GND VC1A C1A VC1B C1B mbd100 Fig 7. Typical waveforms for PLL using phase comparator 1; loop-locked at f0 8.3.2 Phase Comparator 2 (PC2) This is a positive edge-triggered phase and frequency detector. When the PLL is using this comparator, the loop is controlled by positive signal transitions and the duty cycles of SIG_IN and COMP_IN are not important.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO V CC up Icp VCC PC2_OUT Icp up C2 PC2_OUT R3' down VC2_OUT Icp ∆ Φ = ΦPC_IN down pulse overlap of approximately 15 ns mbd046 a. At every ∆Φ, even at zero ∆Φ both switches are closed simultaneously for a short period (typically 15 ns). Fig 8. C2 mbd099 b. Comparable voltage-controlled switch The current switch charge pump output of PC2 +Icp VCC VDEM_OUT(AV) Icp × R 0 0.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO When the frequency of SIG_IN is higher than that of COMP_IN, the source output driver is held ‘ON’ for most of the input signal cycle time and for the remainder of the cycle time both drivers are ‘OFF’ (3-state). If the SIG_IN frequency is lower than the COMP_IN frequency, then it is the sink driver that is held ‘ON’ for most of the cycle.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO 2.75 2.75 VCO_IN VCO_IN (1) 2.50 2.50 (1) (2) 2.25 −25 0 phase error (ns) 2.25 −25 25 0 phase error (ns) 001aak444 25 001aak445 (1) Due to parasitic capacitance on PC2_OUT. (2) Backlash time (dead zone). a. Response with traditional voltage-switch charge-pump PC2_OUT (74HCT4046A). b. Response with current switch charge-pump PC2_OUT as applied in the 74HCT9046A. Fig 11.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO Using this equivalent resistance R3' for the filter design the voltage can now be expressed as a transfer function of PC2; assuming ripple (fr = fi) is suppressed, as: 5 K PC2 = ------ ( V ⁄ r ) 4π Again this illustrates the supply voltage independent behavior of PC2. 8.4 Loop filter component selection Examples of PC2 combined with a passive filter are shown in Figure 12 and 13.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO A Icp F(jω) Icp 17 Rbias OUTPUT 1/Aτ O −1/τ2 R4 INPUT m 1 C2 1/ Aτ 1 / Aτ2 1 001aak446 a. Simple loop filter for PC2 with damping R bias τ 1 = ------------ × C2 = R3‘ × C2 17 ω 001aak448 001aak447 b. Amplitude characteristic 1 + jωτ 2 F ( jω ) = ---------------------------1 ⁄ A + jωτ 1 c. Pole zero diagram A = DC gain limit, due to leakage τ 2 = R4 × C2 Fig 13. Simple loop filter for PC2 with damping 9.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO 10. Recommended operating conditions Table 4. Operating conditions Symbol Parameter VCC Conditions Min Typ Max Unit supply voltage 4.5 5.0 5.5 V VI input voltage 0 - VCC V VO output voltage 0 - Tamb ambient temperature −40 ∆t/∆V input transition rise and fall rate pin INH; VCC = 4.5 V - 1.67 VCC V +125 °C 139 ns/V 11. Static characteristics Table 5.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO Table 5. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VOH HIGH-level output voltage pin VCO_OUT; VCC = 4.5 V; VI = VIH or VIL VOL LOW-level output voltage Min Typ Max Unit IO = −20 µA 4.4 4.5 - V IO = −4.0 mA 3.98 4.32 - V pin VCO_OUT; VCC = 4.5 V; VI = VIH or VIL IO = 20 µA - 0 0.1 V IO = 4.0 mA - 0.15 0.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO Table 5. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VOH HIGH-level output voltage pins PCP_OUT and PCn_OUT; VCC = 4.5 V; VI = VIH or VIL VOL LOW-level output voltage Min Typ Max Unit IO = −20 µA 4.4 - - V IO = −4.0 mA 3.84 - - V pins PCP_OUT and PCn_OUT; VCC = 4.5 V; VI = VIH or VIL IO = 20 µA - - 0.1 V IO = 4.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO Table 5. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VOH HIGH-level output voltage pins PCP_OUT and PCn_OUT; IO = −20 µA 4.4 - - V IO = −4.0 mA 3.7 - - V IO = 20 µA - - 0.1 V IO = 4.0 mA - - 0.4 V - - ±45 µA VCC = 4.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO mbd108 mga956 - 1 800 II RI (kΩ) ∆VI 600 400 VCC = 4.5 V 200 self-bias operating point VI Fig 14. Typical input resistance curve at SIG_IN and COMP_IN 5.5 V 0 (0.5 VCC) − 0.25 VI (V) (0.5 VCC) + 0.25 Fig 15. Input resistance at SIG_IN; COMP_IN with ∆VI = 0.5 V at self-bias point mga957 mga958 60 5 VCC = 5.5V 0.5 VCC Voffset (mV) 40 4.5 V II (µA) 20 VCC = 4.5 V 0 0 4.5 V −5 (0.5 VCC) − 0.25 5.5 V −20 5.5 V 0.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO 12. Dynamic characteristics Table 6. Dynamic characteristics[1] GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Symbol Parameter Conditions Min Typ Max Unit SIG_IN, COMP_IN to PC1_OUT; - 23 40 ns - 35 68 ns Tamb = 25 °C Phase comparator section tpd propagation delay VCC = 4.5 V; see Figure 18 SIG_IN, COMP_IN to PCP_OUT; VCC = 4.5 V; see Figure 18 ten enable time SIG_IN, COMP_IN to PC2_OUT; VCC = 4.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO Table 6. Dynamic characteristics[1] …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Symbol ∆f/∆T Parameter Conditions frequency variation with temperature Min Typ Max Unit - 0.06 - %/K - - 60 ns - - 102 ns SIG_IN, COMP_IN to PC2_OUT; VCC = 4.5 V; see Figure 19 - - 84 ns SIG_IN, COMP_IN to PC2_OUT; - - 98 ns - - 22 ns VCC = 4.5 V; VVCO_IN = 0.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO SIG_IN input VM COMP_IN input VM tPHZ tPZH tPLZ tPZL 90% PC2_OUT output VM 10% mga941 VM = 0.5VCC; VI = GND to VCC. Fig 19. Waveforms showing the enable and disable times for PC2_OUT mbd115 20 ∆f (%) ∆f (%) mbd116 15 10 10 5 0 0 VCC = −5 5.5 V −10 VCC = −10 5.5 V 4.5 V 4.5 V −20 −50 0 50 100 150 Tamb (°C) a. R1 = 3 kΩ; R2 = ∞ Ω; C1 = 100 pF. −15 −50 0 50 100 150 Tamb (°C) b.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO mbd124 10 VCC = ∆f (%) 5.5 V 4.5 V ∆f (%) mbd117 15 10 5 5 VCC = 0 0 5.5 V −5 −10 −5 −15 −10 −50 0 50 100 150 Tamb (°C) a. R1 = 300 kΩ; R2 = ∞ Ω; C1 = 100 pF. −20 −50 4.5 V 0 50 100 150 Tamb (°C) b. R1 = ∞ Ω; R2 = 3 kΩ; C1 = 100 pF. Fig 21. Frequency stability of the VCO as a function of ambient temperature with supply voltage as a parameter mbd118 8 mbd119 10 ∆f (%) ∆f (%) 4 5 0 0 −4 VCC = 5.5 V −8 VCC = 4.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO mbd112 30 mbd113 30 fVCO fVCO (MHz) (kHz) VCC = 4.5 V 20 5.5 V 20 VCC = 4.5 V 10 10 5.5 V 0 0 2 4 0 6 0 2 4 VVCO_IN (V) a. R1 = 4.3 kΩ; C1 = 39 pF. b. 400 f fVCO (kHz) R1 = 4.3 kΩ; C1 = 100 nF. mbd111 mbd120 800 6 VVCO_IN (V) VCO (Hz) VCC = 5.5 V VCC = 5.5 V 300 600 4.5 V frequency 4.5 V frequency 400 200 200 100 0 0 0 2 4 6 0 2 4 c. R1 = 300 kΩ; C1 = 39 pF. 6 VVCO_IN (V) VVCO_IN (V) d.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO mbd114 4 mga937 C1 = 1 µF 4.5 V 5.5 V fVCO (%) f (MHz) C1 = 39 pF 0 f2 4.5 V f0 f' 0 −4 f1 V min 5.5 V V −8 max 0.5 VCC 1 10 10 2 VVCO_IN (V) 3 R1 (kΩ) 10 R2 = ∞ Ω and ∆V = 0.5 V f1 + f2 f‘ 0 = ----------------2 f‘ 0 – f 0 f0 linearity = ------------------ × 100 % Fig 24. Definition of VCO frequency linearity: ∆V = 0.5 V over the VCC range Fig 25.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO mbd109 10 3 PDEM (W) VCC = 10 4 10 5 10 4.5 V 5.5 V 102 Rs (kΩ) 10 3 Fig 28. Typical power dissipation as a function of Rs 74HCT9046A_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO 13. Application information This information is a guide for the approximation of values of external components to be used with the 74HCT9046A in a phase-locked-loop system. Values of the selected components should be within the ranges shown in Table 7. Table 7. Survey of components Component Value R1 between 3 kΩ and 300 kΩ R2 between 3 kΩ and 300 kΩ R1 + R2 parallel value > 2.7 kΩ C1 > 40 pF Table 8.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO mga938 f VCO f max f0 2f L due to R1,C1 f min 1.1 V 0.5 VCC VCC−1.1 V VCC VCO_IN a. Operating without offset; f0 = center frequency; 2fL = frequency lock range. mga939 f VCO f max f0 due to R1,C1 2fL f min f off 0.6fL due to R2,C1 1.1 V 0.5 VCC VCC−1.1 V VCC VCO_IN b. Operating with offset; f0 = center frequency; 2fL = frequency lock range. Fig 29.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO 13.1 Filter design considerations for PC1 and PC2 of the 74HCT9046A Figure 30 shows some examples of passive and active filters to be used with the phase comparators of the 74HCT9046A. Transfer functions of phase comparators and filters are given in Table 9. Table 9.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO AMPLITUDE CHARACTERISTIC PC1 CIRCUIT POLE ZERO DIAGRAM F(jω) R3 X 1/ τ 1 1/ τ 1 C2 (a) F(jω) R3 1/ τ 2 C3 1/ τ 3 O 1/ τ 2 R4 1/ τ 1 τ 2 C2 X 1 τ1 τ2 (b) A C3 1/ τ 2 C2 R4 1/ τ 3 O 1/ τ 2 1/ A τ 1 R3 X 1/ A τ 1 A (c) PC2 A R3' 1/ τ 2 1/ τ 3 R4 AR3' 1/A τ 1 C2 O 1/ τ 2 X 1/ A τ 1 O 1/ τ 2 X 1/ A τ 1 (d) A C3 1/ τ 2 C2 R4 R3' A 1/ τ 3 1/A τ 1 (e) mbd107 Fig 30.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO mbd103 108 f0 (Hz) 107 106 105 104 (1) (2) (3) (4) (5) (6) (7) (8) 103 102 10 1 10 102 103 104 105 106 107 C1 (pF) VCC = 5.5 V; R1 = 3 kΩ. VCC = 4.5 V; R1 = 3 kΩ. VCC = 5.5 V; R1 = 10 kΩ. VCC = 4.5 V; R1 = 10 kΩ. VCC = 5.5 V; R1 = 150 kΩ. VCC = 4.5 V; R1 = 150 kΩ. VCC = 5.5 V; R1 = 300 kΩ. VCC = 4.5 V; R1 = 300 kΩ. R2 = ∞ Ω; VVCO_IN = 0.5VCC; INH = GND; Tamb = 25 °C. Fig 31.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO mbd104 108 foff (Hz) 107 106 105 104 (1) 103 (2) 102 (3) (4) 10 1 10 102 103 104 105 106 107 C1 (pF) VCC = 4.5 V to 5.5 V; R1 = 3 kΩ. VCC = 4.5 V to 5.5 V; R1 = 10 kΩ. VCC = 4.5 V to 5.5 V; R1 = 150 kΩ. VCC = 4.5 V to 5.5 V; R1 = 300 kΩ. R1 = ∞ Ω; VVCO_IN = 0.5VCC; INH = GND; Tamb = 25 °C. Fig 32. Typical value of frequency offset as a function of C1 mbd105 108 2fL (Hz) 107 106 105 104 103 VCC = 102 5.5 V 4.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO 13.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO 5 K p = ------------ = 0.4 V ⁄ r 4×π Using PC2 with the passive filter as shown in Figure 34 results in a high gain loop with the same performance as a loop with an active filter. Hence loop filter equations as for a high gain loop should be used.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO 3 5 5 ω n = --- = ------------- = 5 × 10 r ⁄ s t 0.001 Rewriting the equation for natural frequency results in: K p × Kv × Kn τ 1 = -------------------------------2 ( ωn ) The maximum overshoot occurs at Nmax = 30; hence Kn = 1⁄30: 6 0.4 × 2.24 × 10 τ 1 = -------------------------------------- = 0.0012 2 5000 × 30 When C2 = 470 nF, it follows: τ 0.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO Kp 100 kHz OSCILLATOR "HCU04" DIVIDE BY 10 "190" 14 Kf PHASE COMPARATOR PC2 R3' 13 15 Φu 9 4 VCO fOUT (1) 3 R4 11 C3 Rbias Kn 1 MHz Ko C2 R1 12 6 7 5 R2 C1 PROGRAMMABLE DIVIDER "4059" mbd098 (1) R3’ = fictive resistance R bias 17 R3’ = -----------C1 = 100 pF C2 = 470 nF C3 = 39 nF R1 = 30 kΩ R2 = 30 kΩ R3' = 2550 Ω Rbias = 43 kΩ R4 = 600 Ω Fig 34. Frequency synthesizer mga959 1.6 ∆ωe(t) ∆ωe/ωn ζ = 0.3 1.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO mga952 3.1 N = 30 proportional to output frequency (MHz) N stepped from 29 to 30 2.9 step input 2.1 N stepped from 21 to 20 2.0 1.9 0 0.5 1.0 1.5 2.0 2.5 time (ms) Fig 36. Frequency compared to the time response Since the output frequency is proportional to the VCO control voltage, the PLL frequency response can be observed with an oscilloscope by monitoring pin VCO_IN of the VCO.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO 14. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO 15. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model PLL Phase Locked Loop VCO Voltage Controlled Oscillator 16. Revision history Table 12.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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74HCT9046A NXP Semiconductors PLL with band gap controlled VCO 19. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.3.1 8.3.2 8.4 9 10 11 12 13 13.1 13.2 13.3 14 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . .