Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Inverter Inverter 74LV DHVQFN 14 (2.5x3)

1. General description

The 74LV04 is a low-voltage Si-gate CMOS device that is pin and function compatible with

74HC04 and 74HCT04.

The 74LV04 provides six inverting buffers.

2. Features

■ Wide operating voltage: 1.0 V to 5.5 V

■ Optimized for low voltage applications: 1.0 V to 3.6 V

■ Accepts TTL input levels between V

= 2.7 V and V

= 3.6 V

■ Typical output ground bounce < 0.8 V at V

= 3.3 V and T

amb

= 25 °C

■ Typical HIGH-level output voltage (V

) undershoot: > 2 V at V

= 3.3 V and

amb

=25°C

■ ESD protection:

◆ HBM JESD22-A114E exceeds 2000 V

◆ MM JESD22-A115-A exceeds 200 V

■ Multiple package options

■ Speciﬁed from −40 °Cto+85°C and from −40 °C to +125 °C

3. Ordering information

74LV04

Hex inverter

Rev. 03 — 4 December 2007 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74LV04N −40 °C to +125 °C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1

74LV04D −40 °C to +125 °C SO14 plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

74LV04DB −40 °C to +125 °C SSOP14 plastic shrink small outline package; 14 leads;

body width 5.3 mm

SOT337-1

74LV04PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

74LV04BQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very

thin quad ﬂat package; no leads; 14 terminals;

body 2.5 × 3 × 0.85 mm

SOT762-1

Summary of content (15 pages)

PAGE 1
74LV04 Hex inverter Rev. 03 — 4 December 2007 Product data sheet 1. General description The 74LV04 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC04 and 74HCT04. The 74LV04 provides six inverting buffers. 2. Features ■ ■ ■ ■ ■ Wide operating voltage: 1.0 V to 5.5 V Optimized for low voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Typical output ground bounce < 0.8 V at VCC = 3.
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74LV04 NXP Semiconductors Hex inverter 4. Functional diagram 1 1 1A 1Y 2 3 2A 2Y 4 3 5 5 3A 3Y 6 9 4A 4Y 8 11 5A 5Y 10 13 6A 6Y 12 9 11 13 1 2 1 4 1 6 1 8 1 10 1 12 Y A mna343 mna342 Fig 1. Logic symbol mna341 Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 5. Pinning information 5.
PAGE 3
74LV04 NXP Semiconductors Hex inverter 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A 1 data input 1Y 2 data output 2A 3 data input 2Y 4 data output 3A 5 data input 3Y 6 data output GND 7 ground (0 V) 4Y 8 data output 4A 9 data input 5Y 10 data output 5A 11 data input 6Y 12 data output 6A 13 data input VCC 14 supply voltage 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level.
PAGE 4
74LV04 NXP Semiconductors Hex inverter Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
PAGE 5
74LV04 NXP Semiconductors Hex inverter 9. Static characteristics Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter HIGH-level input voltage VIH LOW-level input voltage VIL VOH HIGH-level output voltage LOW-level output voltage VOL Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max VCC = 1.2 V 0.9 - - 0.9 - V VCC = 2.0 V 1.4 - - 1.4 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 4.5 V to 5.5 V 0.
PAGE 6
74LV04 NXP Semiconductors Hex inverter 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure 7. Symbol Parameter propagation delay tpd −40 °C to +85 °C Conditions Min Max Min Max VCC = 1.2 V - 40 - - - ns VCC = 2.0 V - 14 20 - 25 ns 15 - 19 ns nA to nY; see Figure 6 - 10 VCC = 3.0 V to 3.6 V; CL = 15 pF [3] - 6 - - - ns VCC = 3.0 V to 3.6 V [3] - 8 12 - 15 ns - - 9 - 11 ns - 21 - - - pF VCC = 4.
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4LV04 NXP Semiconductors Hex inverter Table 8. Measurement points Supply voltage Input Output VCC VM VM < 2.7 V 0.5VCC 0.5VCC 2.7 V to 3.6 V 1.5 V 1.5 V ≥ 4.5 V 0.5VCC 0.5VCC VCC PULSE GENERATOR VI VO D.U.T. RT CL 50 pF RL 1 kΩ 001aaa663 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. Fig 7.
PAGE 8
74LV04 NXP Semiconductors Hex inverter 12. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.
PAGE 9
74LV04 NXP Semiconductors Hex inverter SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.
PAGE 10
74LV04 NXP Semiconductors Hex inverter SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.
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74LV04 NXP Semiconductors Hex inverter TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.
PAGE 12
74LV04 NXP Semiconductors Hex inverter DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.1 2.9 1.65 1.35 2.
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74LV04 NXP Semiconductors Hex inverter 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11.
PAGE 14
74LV04 NXP Semiconductors Hex inverter 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
PAGE 15
74LV04 NXP Semiconductors Hex inverter 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . .