Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Gate AND gate 74LV SO 14

1. General description

The 74LV08 is a low-voltage Si-gate CMOS device that is pin and function compatible with

74HC08 and 74HCT08.

The 74LV08 provides a quad 2-input AND function.

2. Features

n Wide operating voltage: 1.0 V to 5.5 V

n Optimized for low voltage applications: 1.0 V to 3.6 V

n Accepts TTL input levels between V

= 2.7 V and V

= 3.6 V

n Typical output ground bounce < 0.8 V at V

= 3.3 V and T

amb

= 25 °C

n Typical HIGH-level output voltage (V

) undershoot: > 2 V at V

= 3.3 V and

amb

=25°C

n ESD protection:

u HBM JESD22-A114E exceeds 2000 V

u MM JESD22-A115-A exceeds 200 V

n Multiple package options

n Speciﬁed from −40 °Cto+85°C and from −40 °C to +125 °C

3. Ordering information

74LV08

Quad 2-input AND gate

Rev. 03 — 6 April 2009 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74LV08N −40 °C to +125 °C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1

74LV08D −40 °C to +125 °C SO14 plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

74LV08DB −40 °C to +125 °C SSOP14 plastic shrink small outline package; 14 leads;

body width 5.3 mm

SOT337-1

74LV08PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

Summary of content (13 pages)

PAGE 1
74LV08 Quad 2-input AND gate Rev. 03 — 6 April 2009 Product data sheet 1. General description The 74LV08 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC08 and 74HCT08. The 74LV08 provides a quad 2-input AND function. 2. Features n n n n n Wide operating voltage: 1.0 V to 5.5 V Optimized for low voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Typical output ground bounce < 0.8 V at VCC = 3.
PAGE 2
74LV08 NXP Semiconductors Quad 2-input AND gate 4. Functional diagram 1 & 3 & 6 2 1 1A 2 1B 4 2A 5 2B 9 3A 10 3B 12 4A 13 4B 1Y 3 4 2Y 6 5 3Y 8 9 A Y & 8 B 10 4Y mna221 11 12 mna222 & 11 13 mna223 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 5. Pinning information 5.
PAGE 3
74LV08 NXP Semiconductors Quad 2-input AND gate 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A, 2A, 3A, 4A 1, 4, 9, 12 data input 1B, 2B, 3B, 4B 2, 5, 10, 13 data input 1Y, 2Y, 3Y, 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) VCC 14 supply voltage 6. Functional description Table 3. Function selection[1] Input Output nA nB nY L X L X L L H H H [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care 7. Limiting values Table 4.
PAGE 4
74LV08 NXP Semiconductors Quad 2-input AND gate 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply Conditions voltage[1] Min Typ Max Unit 1.0 3.3 5.5 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature −40 +25 +125 °C ∆t/∆V input transition rise and fall rate VCC = 1.0 V to 2.0 V - - 500 ns/V VCC = 2.0 V to 2.
PAGE 5
74LV08 NXP Semiconductors Quad 2-input AND gate Table 6. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter VOL −40 °C to +85 °C Conditions LOW-level output voltage Min Typ[1] −40 °C to +125 °C Unit Max Min Max VI = VIH or VIL IO = 100 µA; VCC = 1.2 V - 0 - - - V IO = 100 µA; VCC = 2.0 V - 0 0.2 - 0.2 V IO = 100 µA; VCC = 2.7 V - 0 0.2 - 0.2 V IO = 100 µA; VCC = 3.0 V - 0 0.2 - 0.2 V IO = 100 µA; VCC = 4.5 V - 0 0.
PAGE 6
74LV08 NXP Semiconductors Quad 2-input AND gate 11. Waveforms VI VM nA, nB input GND t PLH t PHL VOH VM nY output VOL mna224 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Table 8. The input (nA, nB) to output (nY) propagation delays Measurement points Supply voltage Input Output VCC VM VM < 2.7 V 0.5VCC 0.5VCC 2.7 V to 3.6 V 1.5 V 1.5 V ≥ 4.5 V 0.5VCC 0.5VCC VCC PULSE GENERATOR VI VO D.U.T.
PAGE 7
4LV08 NXP Semiconductors Quad 2-input AND gate 12. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.
PAGE 8
74LV08 NXP Semiconductors Quad 2-input AND gate SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.
PAGE 9
74LV08 NXP Semiconductors Quad 2-input AND gate SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.
PAGE 10
74LV08 NXP Semiconductors Quad 2-input AND gate TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.
PAGE 11
74LV08 NXP Semiconductors Quad 2-input AND gate 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11.
PAGE 12
74LV08 NXP Semiconductors Quad 2-input AND gate 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
PAGE 13
74LV08 NXP Semiconductors Quad 2-input AND gate 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . .