Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Receiver, transceiver TSSOP 20

1. General description

The 74LV245 is a low-voltage Si-gate CMOS device that is pin and function compatible

with 74HC245 and 74HCT245.

The 74LV245 is an octal transceiver with non-inverting 3-state bus compatible outputs in

both send and receive directions. A send/receive (DIR) input controls direction, and an

output enable (OE) input makes easy cascading possible. Pin OE controls the outputs so

that the buses are effectively isolated.

2. Features

n Wide operating voltage: 1.0 V to 5.5 V

n Optimized for low voltage applications: 1.0 V to 3.6 V

n Accepts TTL input levels between V

= 2.7 V and V

= 3.6 V

n Typical output ground bounce < 0.8 V at V

= 3.3 V and T

amb

= 25 °C

n Typical HIGH-level output voltage (V

) undershoot: > 2 V at V

= 3.3 V and

amb

=25°C

n ESD protection:

u HBM JESD22-A114E exceeds 2000 V

u MM JESD22-A115-A exceeds 200 V

n Multiple package options

n Speciﬁed from −40 °Cto+85°C and from −40 °C to +125 °C

3. Ordering information

74LV245

Octal bus transceiver; 3-state

Rev. 03 — 15 April 2009 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74LV245N −40 °C to +125 °C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1

74LV245D −40 °C to +125 °C SO20 plastic small outline package; 20 leads;

body width 7.5 mm

SOT163-1

74LV245DB −40 °C to +125 °C SSOP20 plastic shrink small outline package; 20 leads;

body width 5.3 mm

SOT339-1

74LV245PW −40 °C to +125 °C TSSOP20 plastic thin shrink small outline package; 20 leads;

body width 4.4 mm

SOT360-1

Summary of content (15 pages)

PAGE 1
74LV245 Octal bus transceiver; 3-state Rev. 03 — 15 April 2009 Product data sheet 1. General description The 74LV245 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC245 and 74HCT245. The 74LV245 is an octal transceiver with non-inverting 3-state bus compatible outputs in both send and receive directions. A send/receive (DIR) input controls direction, and an output enable (OE) input makes easy cascading possible.
PAGE 2
74LV245 NXP Semiconductors Octal bus transceiver; 3-state 4. Functional diagram 1 DIR OE 2 B0 3 19 3EN1 3EN2 1 14 18 3 17 4 16 13 5 15 6 14 7 13 8 12 A6 12 A7 B7 11 9 Logic symbol Fig 2. IEC logic symbol 74LV245_3 Product data sheet 11 mna175 mna174 Fig 1. 2 A5 B6 9 G3 2 B5 8 15 A4 B4 7 1 16 A3 B3 6 17 A2 B2 5 18 A1 B1 4 19 A0 © NXP B.V. 2009. All rights reserved. Rev.
PAGE 3
74LV245 NXP Semiconductors Octal bus transceiver; 3-state 5. Pinning information 5.1 Pinning 74LV245 74LV245 DIR 1 20 VCC DIR 1 20 VCC A0 2 19 OE A0 2 19 OE A1 3 18 B0 A1 3 18 B0 A2 4 17 B1 A2 4 17 B1 A3 5 16 B2 A3 5 16 B2 A4 6 15 B3 A4 6 15 B3 A5 7 14 B4 A5 7 14 B4 A6 8 13 B5 A6 8 13 B5 A7 9 12 B6 A7 9 12 B6 GND 10 11 B7 GND 10 11 B7 001aaj962 Fig 3. 001aaj963 Pin configuration DIP20, SO20 Fig 4. Pin configuration SSOP20, TSSOP20 5.
PAGE 4
74LV245 NXP Semiconductors Octal bus transceiver; 3-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit −0.5 +7.0 V - ±20 mA - ±50 mA - ±35 mA mA IIK input clamping current VI < −0.5 V or VI > VCC + 0.5 V [1] IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V [1] IO output current VO = −0.
PAGE 5
74LV245 NXP Semiconductors Octal bus transceiver; 3-state 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter HIGH-level input voltage VIH LOW-level input voltage VIL VOH HIGH-level output voltage LOW-level output voltage VOL −40 °C to +85 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max VCC = 1.2 V 0.9 - - 0.9 - V VCC = 2.0 V 1.4 - - 1.4 - V VCC = 2.
PAGE 6
74LV245 NXP Semiconductors Octal bus transceiver; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7. Symbol Parameter propagation delay tpd −40 °C to +85 °C Conditions enable time Min Max Min Max VCC = 1.2 V - 45 28 - - ns VCC = 2.0 V - 15 28 - 34 ns 19 - 24 ns An, Bn to Bn, An; see Figure 5 - 11 VCC = 3.0 V to 3.6 V; CL = 15 pF [3] - 7 - - - ns VCC = 3.0 V to 3.
PAGE 7
4LV245 NXP Semiconductors Octal bus transceiver; 3-state 11. Waveforms VI An, Bn input VM VM GND tPLH tPHL VOH VM Bn, An output VM VOL mna176 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 5.
PAGE 8
74LV245 NXP Semiconductors Octal bus transceiver; 3-state VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC VI RL VO G DUT RT CL RL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times.
PAGE 9
74LV245 NXP Semiconductors Octal bus transceiver; 3-state 12. Package outline DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1 ME seating plane D A2 A A1 L c e Z b1 w M (e 1) b MH 11 20 pin 1 index E 1 10 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 0.36 0.23 26.92 26.54 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.014 0.009 1.
PAGE 10
74LV245 NXP Semiconductors Octal bus transceiver; 3-state SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 10 1 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.
PAGE 11
74LV245 NXP Semiconductors Octal bus transceiver; 3-state SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm D SOT339-1 E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 w M bp e detail X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 7.4 7.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.
PAGE 12
74LV245 NXP Semiconductors Octal bus transceiver; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.
PAGE 13
74LV245 NXP Semiconductors Octal bus transceiver; 3-state 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11.
PAGE 14
74LV245 NXP Semiconductors Octal bus transceiver; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
PAGE 15
74LV245 NXP Semiconductors Octal bus transceiver; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . .