Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Gate and inverter NAND gate 74LVC TSSOP 14

1. General description

The 74LVC00A provides four 2-input NAND gates.

Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall

times.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

devices as translators in mixed 3.3 V and 5 V applications.

2. Features and benefits

 5 V tolerant inputs for interfacing with 5 V logic

 Wide supply voltage range from 1.2 V to 3.6 V

 CMOS low-power consumption

 Direct interface with TTL levels

 Complies with JEDEC standard:

 JESD8-7A (1.65 V to 1.95 V)

 JESD8-5A (2.3 V to 2.7 V)

 JESD8-C/JESD36 (2.7 V to 3.6 V)

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-B exceeds 200 V

 CDM JESD22-C101E exceeds 1000 V

 Specified from −40 °C to +85 °C and −40 °C to +125 °C

3. Ordering information

74LVC00A

Quad 2-input NAND gate

Rev. 7 — 25 April 2012 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74LVC00AD −40 °Cto+125°C SO14 plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

74LVC00ADB −40 °Cto+125°C SSOP14 plastic shrink small outline package; 14 leads;

body width 5.3 mm

SOT337-1

74LVC00APW −40 °Cto+125°C TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

74LVC00ABQ −40 °Cto+125°C DHVQFN14 plastic dual in-line compatible thermal enhanced very

thin quad flat package; no leads; 14 terminals;

body 2.5 × 3 × 0.85 mm

SOT762-1

Summary of content (14 pages)

PAGE 1
74LVC00A Quad 2-input NAND gate Rev. 7 — 25 April 2012 Product data sheet 1. General description The 74LVC00A provides four 2-input NAND gates. Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. 2.
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74LVC00A NXP Semiconductors Quad 2-input NAND gate 4. Functional diagram 1 1 1A 2 1B 1Y 3 4 2A 5 2B 2Y 6 9 3A 10 3B 3Y 8 12 4A 13 4B 4Y 11 2 4 5 9 10 12 13 & 3 & 6 & 8 A Y 11 & B mna212 Fig 1. mna211 mna246 Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram for one gate 5. Pinning information 1 1A terminal 1 index area 14 VCC 5.
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74LVC00A NXP Semiconductors Quad 2-input NAND gate 6. Functional description Table 3. Function selection[1] Input Output nA nB nY L X H X L H H H L [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
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74LVC00A NXP Semiconductors Quad 2-input NAND gate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter −40 °C to +85 °C Conditions Min HIGH-level input voltage VIH LOW-level input voltage VIL VOH HIGH-level output voltage LOW-level output voltage VOL Typ[1] −40 °C to +125 °C Max Min Unit Max VCC = 1.2 V 1.08 - - 1.08 - V VCC = 1.65 V to 1.95 V 0.65 × VCC - - 0.
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74LVC00A NXP Semiconductors Quad 2-input NAND gate 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7. Symbol Parameter propagation delay tpd −40 °C to +85 °C Conditions Min Max Min Max - 12 - - - ns VCC = 1.65 V to 1.95 V 0.3 3.8 8.4 0.3 9.7 ns VCC = 2.3 V to 2.7 V 1.0 2.2 4.8 1.0 5.7 ns [2] nA, nB to nY; see Figure 6 VCC = 1.
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74LVC00A NXP Semiconductors Quad 2-input NAND gate tW VI 90 % negative pulse VM VM 10 % 0V tf tr tr tf VI 90 % positive pulse VM VM 10 % 0V tW VCC PULSE GENERATOR VI VO DUT RT CL RL 001aaf615 Test data is given in Table 8. Definitions for test circuit: RL = Load resistance CL = Load capacitance including jig and probe capacitance RT = Termination resistance should be equal to output impedance Zo of the pulse generator Fig 7. Table 8.
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4LVC00A NXP Semiconductors Quad 2-input NAND gate 12. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.
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74LVC00A NXP Semiconductors Quad 2-input NAND gate SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.
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74LVC00A NXP Semiconductors Quad 2-input NAND gate TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.
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74LVC00A NXP Semiconductors Quad 2-input NAND gate DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.1 2.9 1.
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74LVC00A NXP Semiconductors Quad 2-input NAND gate 13. Abbreviations Table 9. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC00A v.7 20120425 Product data sheet - 74LVC00A v.6 - 74LVC00A v.5 Modifications: 74LVC00A v.
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74LVC00A NXP Semiconductors Quad 2-input NAND gate 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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74LVC00A NXP Semiconductors Quad 2-input NAND gate Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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74LVC00A NXP Semiconductors Quad 2-input NAND gate 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . .