Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Buffer, driver SO 14

1. General description

The 74LVC07A provides six non-inverting buffers. The outputs are open-drain and can be

connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH

wired-AND functions.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

devices as translators in mixed 3.3 V and 5 V applications.

2. Features and benefits

 5 V tolerant inputs and outputs (open-drain) for interfacing with 5 V logic

 Wide supply voltage range from 1.2 V to 5.5 V

 CMOS low power consumption

 Direct interface with TTL levels

 Inputs accept voltages up to 5 V

 Complies with JEDEC standard:

 JESD8-7A (1.65 V to 1.95 V)

 JESD8-5A (2.3 V to 2.7 V)

 JESD8-C/JESD36 (2.7 V to 3.6 V)

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-B exceeds 200 V

 CDM JESD22-C101E exceeds 1000 V

 Specified from 40 C to +85 C and 40 C to +125 C

3. Ordering information

74LVC07A

Hex buffer with open-drain outputs

Rev. 5 — 27 October 2011 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74LVC07AD 40 Cto+125C SO14 plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

74LVC07APW 40 Cto+125C TSSOP14 plastic thin small outline package; 14 leads;

body width 4.4 mm

SOT402-1

74LVC07ABQ 40 Cto+125C DHVQFN14 plastic dual in-line compatible thermal enhanced very

thin quad flat package; no leads; 14 terminals;

body 2.5  3  0.85 mm

SOT762-1

Summary of content (14 pages)

PAGE 1
74LVC07A Hex buffer with open-drain outputs Rev. 5 — 27 October 2011 Product data sheet 1. General description The 74LVC07A provides six non-inverting buffers. The outputs are open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. 2.
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74LVC07A NXP Semiconductors Hex buffer with open-drain outputs 4. Functional diagram 1 1A 1Y 2 3 2A 2Y 4 1A 2A 5 3A 3Y 6 3A 9 4A 4Y 8 4A 11 5A 5Y 10 5A 13 6A 6Y 12 6A 1 1 2 3 1 4 5 1 6 9 1 8 11 1 10 13 1 2Y 3Y 4Y 12 Y 5Y A 6Y GND mna534 mna535 Fig 1. 1Y Logic symbol Fig 2. mna533 IEC logic symbol Fig 3. Logic diagram for one gate 5. Pinning information 5.
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74LVC07A NXP Semiconductors Hex buffer with open-drain outputs 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A, 2A, 3A, 4A, 5A, 6A 1, 3, 5, 9, 11, 13 data input 1Y, 2Y, 3Y, 4Y, 5Y, 6Y 2, 4, 6, 8, 10, 12 data output GND 7 ground (0 V) VCC 14 supply voltage 6. Functional description Table 3. Function selection [1] Input Output nA nY L L H Z [1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state 7. Limiting values Table 4.
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74LVC07A NXP Semiconductors Hex buffer with open-drain outputs 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions VCC supply voltage VI input voltage VO output voltage Tamb ambient temperature t/V input transition rise and fall rate Min Typ Max Unit 1.65 - 5.5 V functional 1.2 - - V 0 - 5.5 V active mode 0 - VCC V high-impedance mode 0 - 5.5 V 40 - +125 C VCC = 1.65 V to 2.
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74LVC07A NXP Semiconductors Hex buffer with open-drain outputs Table 6. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions Typ[1] Min 40 C to +125 C Max Min Unit Max ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - 0.1 10 - 40 A ICC additional supply current per input pin; VI = VCC  0.6 V; IO = 0 A; - 5 500 - 5000 A CI input capacitance - 5.
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74LVC07A NXP Semiconductors Hex buffer with open-drain outputs 11. Waveforms VI VM nA input VM GND t PLZ t PZL VCC nY output VM VX VOL mna528 Measurements points are given in Table 8. Logic level: VOL is a typical output voltage level that occurs with the output load. Fig 6. Table 8. The input (nA) to output (nY) propagation delays Measurement points Supply voltage Input Output VCC VM VX < 2.7 V 0.5  VCC VOL + 0.15 V  2.7 V to 3.6 V 1.5 V VOL + 0.3 V  4.5 V to 5.5 V 0.
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4LVC07A NXP Semiconductors Hex buffer with open-drain outputs VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC VI RL VO G DUT RT RL CL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times.
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74LVC07A NXP Semiconductors Hex buffer with open-drain outputs 12. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.
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74LVC07A NXP Semiconductors Hex buffer with open-drain outputs TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.
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74LVC07A NXP Semiconductors Hex buffer with open-drain outputs DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.
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74LVC07A NXP Semiconductors Hex buffer with open-drain outputs 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC07A v.5 20111027 Product data sheet - 74LVC07A v.4 Modifications: 74LVC07A v.
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74LVC07A NXP Semiconductors Hex buffer with open-drain outputs 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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74LVC07A NXP Semiconductors Hex buffer with open-drain outputs Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.
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74LVC07A NXP Semiconductors Hex buffer with open-drain outputs 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . .