Datasheet

74LVC132A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 7 December 2011 3 of 16
NXP Semiconductors
74LVC132A
Quad 2-input NAND Schmitt trigger
6. Pinning information
6.1 Pinning
6.2 Pin description
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 4. Pin configuration SO14 and TSSOP14 Fig 5. Pin configuration DHVQFN14
74LVC132A
1A V
CC
1B 4B
1Y 4A
2A 4Y
2B 3B
2Y 3A
GND 3Y
001aaf590
1
2
3
4
5
6
7
8
10
9
12
11
14
13
001aaf591
74LVC132A
Transparent top view
2Y 3A
2B 3B
2A 4Y
1Y 4A
GND(1)
1B 4B
GND
3Y
1A V
CC
6 9
5 10
4 11
3 12
2 13
7 8
1
14
terminal 1
index area
Table 2. Pin description
Symbol Pin Description
1A 1 data input
1B 2 data input
1Y 3 data output
2A 4 data input
2B 5 data input
2Y 6 data output
GND 7 ground (0 V)
3Y 8 data output
3A 9 data input
3B 10 data input
4Y 11 data output
4A 12 data input
4B 13 data input
V
CC
14 supply voltage