Datasheet
1. General description
The 74LVC138A is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted
address inputs (A0, A1 and A2) and, when enabled, provides eight mutually exclusive
outputs (Y
0to Y7) that are LOW when selected.
There are three enable inputs: two active LOW (E
1andE2) and one active HIGH (E3).
Every output will be HIGH unless E
1andE2 are LOW and E3 is HIGH.
This multiple enable function allows easy parallel expansion of the device to a 1-of-32
(5 lines to 32 lines) decoder with just four 74LVC138A devices and one inverter. The
74LVC138A can be used as an eight output demultiplexer by using one of the active LOW
enable inputs as the data input and the remaining enable inputs as strobes. Unused
enable inputs must be permanently tied to their appropriate active HIGH or LOW state.
2. Features and benefits
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Demultiplexing capability
Multiple input enable for easy expansion
Ideal for memory chip select decoding
Mutually exclusive outputs
Output drive capability 50 transmission lines at 125 C
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from 40 Cto+85C and from 40 C to +125 C
74LVC138A
3-to-8 line decoder/demultiplexer; inverting
Rev. 5 — 19 October 2011 Product data sheet