Datasheet

74LVC1G10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 10 September 2014 2 of 17
NXP Semiconductors
74LVC1G10
Single 3-input NAND gate
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LVC1G10GW 40 C to +125 C SC-88 plastic surface-mounted package; 6 leads SOT363
74LVC1G10GV 40 C to +125 C SC-74 plastic surface-mounted package (TSOP6); 6 leads SOT457
74LVC1G10GM 40 C to +125 C XSON6 plastic extremely thin small outline package;
no leads; 6 terminals; body 1  1.45  0.5 mm
SOT886
74LVC1G10GF 40 C to +125 C XSON6 plastic extremely thin small outline package;
no leads; 6 terminals; body 1  1  0.5 mm
SOT891
74LVC1G10GN 40 C to +125 C XSON6 extremely thin small outline package; no leads;
6 terminals; body 0.9  1.0  0.35 mm
SOT1115
74LVC1G10GS 40 C to +125 C XSON6 extremely thin small outline package; no leads;
6 terminals; body 1.0  1.0  0.35 mm
SOT1202
Table 2. Marking
Type number Marking code
[1]
74LVC1G10GW YM
74LVC1G10GV YM
74LVC1G10GM YM
74LVC1G10GF YM
74LVC1G10GN YM
74LVC1G10GS YM
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram
001aag686
3
B
6
C
1
A
Y
4
001aag687
&
1
34
6
001aag688
BY
A
C