Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Gate OR gate 74LVC TSSOP 6

1. General description

The 74LVC1G332 provides one 3-input OR function.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

devices as translators in mixed 3.3 V and 5 V applications.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall

time.

This device is fully specified for partial power-down applications using I

OFF

The I

OFF

circuitry disables the output, preventing the damaging backflow current through

the device when it is powered down.

2. Features and benefits

 Wide supply voltage range from 1.65 V to 5.5 V

 High noise immunity

 Complies with JEDEC standard:

 JESD8-7 (1.65 V to 1.95 V)

 JESD8-5 (2.3 V to 2.7 V)

 JESD8B/JESD36 (2.7 V to 3.6 V)

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V

 CDM JESD22-C101-C exceeds 1000 V

 24 mA output drive (V

=3.0V)

 CMOS low power consumption

 Latch-up performance exceeds 250 mA

 Direct interface with TTL levels

 Inputs accept voltages up to 5 V

 Multiple package options

 Specified from 40 C to +85 C and 40 C to +125 C

74LVC1G332

Single 3-input OR gate

Rev. 5 — 10 September 2014 Product data sheet

Summary of content (17 pages)

PAGE 1
74LVC1G332 Single 3-input OR gate Rev. 5 — 10 September 2014 Product data sheet 1. General description The 74LVC1G332 provides one 3-input OR function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall time. This device is fully specified for partial power-down applications using IOFF.
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74LVC1G332 NXP Semiconductors Single 3-input OR gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC1G332GW 40 C to +125 C SC-88 plastic surface-mounted package; 6 leads SOT363 74LVC1G332GV 40 C to +125 C SC-74 plastic surface-mounted package (TSOP6); 6 leads SOT457 74LVC1G332GM 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1  1.45  0.
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74LVC1G332 NXP Semiconductors Single 3-input OR gate 6. Pinning information 6.1 Pinning 74LVC1G332 74LVC1G332 A 1 6 A 1 6 C GND 2 5 VCC C GND 2 5 VCC B 3 4 Y B 3 4 Y A 1 6 C GND 2 5 VCC B 3 4 Y 001aaf475 001aaf474 Transparent top view Transparent top view 001aaf473 Fig 4. 74LVC1G332 Pin configuration SOT363 and SOT457 Fig 5. Pin configuration SOT886 Fig 6. Pin configuration SOT891, SOT1115 and SOT1202 6.2 Pin description Table 3.
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74LVC1G332 NXP Semiconductors Single 3-input OR gate 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
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74LVC1G332 NXP Semiconductors Single 3-input OR gate 10. Static characteristics Table 7. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter HIGH-level input voltage VIH LOW-level input voltage VIL VOH HIGH-level output voltage 40 C to +85 C Conditions VCC = 1.65 V to 1.95 V LOW-level output voltage Min Max Min Max Unit 0.65VCC - - 0.65VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.
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74LVC1G332 NXP Semiconductors Single 3-input OR gate 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter 40 C to +85 C Conditions Min Max Min Max VCC = 1.65 V to 1.95 V 1.5 4.7 17.2 1.5 21.5 ns VCC = 2.3 V to 2.7 V 1.0 3.0 6.2 1.0 7.8 ns VCC = 2.7 V 1.0 3.0 6.0 1.0 7.5 ns VCC = 3.0 V to 3.6 V 1.0 2.6 4.8 1.0 6.2 ns VCC = 4.5 V to 5.5 V 1.0 1.9 3.5 1.0 4.
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4LVC1G332 NXP Semiconductors Single 3-input OR gate Table 9. Measurement points Supply voltage Input Output VCC VM VM 1.65 V to 1.95 V 0.5VCC 0.5VCC 2.3 V to 2.7 V 0.5VCC 0.5VCC 2.7 V 1.5 V 1.5 V 3.0 V to 3.6 V 1.5 V 1.5 V 4.5 V to 5.5 V 0.5VCC 0.5VCC 9(;7 9&& * 9, 5/ 92 '87 57 &/ 5/ PQD Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance.
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74LVC1G332 NXP Semiconductors Single 3-input OR gate 13.
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74LVC1G332 NXP Semiconductors Single 3-input OR gate 14. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC1G332 v.5 20140910 Product data sheet - 74LVC1G332 v.
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74LVC1G332 NXP Semiconductors Single 3-input OR gate 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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74LVC1G332 NXP Semiconductors Single 3-input OR gate Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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NXP Semiconductors 74LVC1G332 Single 3-input OR gate 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . .