Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Gate and inverter XOR gate 74LVC TSSOP 6

1. General description

The 74LVC1G386 provides a 3-input EXCLUSIVE-OR function.

The input can be driven from either 3.3 or 5 V devices. This feature allows the use of

these devices in a mixed 3.3 and 5 V environment.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall

time.

This device is fully speciﬁed for partial power-down applications using I

OFF

. The I

OFF

circuitry disables the output, preventing the damaging backﬂow current through the device

when it is powered down.

2. Features

■ Wide supply voltage range from 1.65 to 5.5 V

■ High noise immunity

■ Complies with JEDEC standard:

◆ JESD8-7 (1.65 V to 1.95 V)

◆ JESD8-5 (2.3 V to 2.7 V)

◆ JESD8B/JESD36 (2.7 V to 3.6 V)

■ ±24 mA output drive (V

= 3.0 V)

■ Latch-up performance exceeds 250 mA

■ CMOS low power consumption

■ Direct interface with TTL levels

■ Inputs accept voltages up to 5 V

■ ESD protection:

◆ HBM EIA/JESD22-A114E exceeds 2000 V

◆ MM EIA/JESD22-A115-A exceeds 200 V.

■ SOT363 and SOT457 package

■ Speciﬁed from −40 to +85 °C and −40 to +125 °C.

3. Ordering information

74LVC1G386

3-input EXCLUSIVE-OR gate

Rev. 02 — 3 September 2007 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74LVC1G386GW −40 °C to +125 °C SC-88 plastic surface-mounted package; 6 leads SOT363

74LVC1G386GV −40 °C to +125 °C SC-74A plastic surface-mounted package (TSOP6); 6 leads SOT457

Summary of content (12 pages)

PAGE 1
74LVC1G386 3-input EXCLUSIVE-OR gate Rev. 02 — 3 September 2007 Product data sheet 1. General description The 74LVC1G386 provides a 3-input EXCLUSIVE-OR function. The input can be driven from either 3.3 or 5 V devices. This feature allows the use of these devices in a mixed 3.3 and 5 V environment. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall time. This device is fully specified for partial power-down applications using IOFF.
PAGE 2
74LVC1G386 NXP Semiconductors 3-input EXCLUSIVE-OR gate 4. Marking Table 2. Marking Type number Marking code 74LVC1G386GW YH 74LVC1G386GV YH 5. Functional diagram 1 3 6 A Y B 1 3 6 4 C =1 4 mnb143 mnb145 Fig 1. Logic symbol Fig 2. IEC logic symbol A B Y C mnb144 Fig 3. Logic diagram 6. Pinning information 6.1 Pinning 74LVC1G386 A 1 6 C GND 2 5 VCC B 3 4 Y 001aag920 Fig 4. Pin configuration 74LVC1G386_2 Product data sheet © NXP B.V. 2007. All rights reserved.
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74LVC1G386 NXP Semiconductors 3-input EXCLUSIVE-OR gate 6.2 Pin description Table 3. Pin description Symbol Pin Description A 1 data input GND 2 ground (0 V) B 3 data input Y 4 data output VCC 5 supply voltage C 6 data input 7. Functional description Table 4. Function table[1] Input Output A B C Y L L L L L L H H L H L H L H H L H L L H H L H L H H L L H H H H [1] H = HIGH voltage level; L = LOW voltage level 8. Limiting values Table 5.
PAGE 4
74LVC1G386 NXP Semiconductors 3-input EXCLUSIVE-OR gate [2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. [3] For SC-74 and SC-88 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. 9. Recommended operating conditions Table 6.
PAGE 5
74LVC1G386 NXP Semiconductors 3-input EXCLUSIVE-OR gate Table 7. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ[1] Max Unit IOFF power-off leakage current VCC = 0 V; VI or VO = 5.5 V - ±0.1 ±10 µA ICC supply current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A - 0.1 10 µA ∆ICC additional supply current per pin; VCC = 2.3 V to 5.5 V; VI = VCC − 0.
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74LVC1G386 NXP Semiconductors 3-input EXCLUSIVE-OR gate 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 6. Symbol Parameter −40 °C to +85 °C Conditions power dissipation capacitance CPD Unit Min Max Min Max VCC = 1.65 V to 1.95 V 2.0 8.0 17.0 2.0 22.0 ns VCC = 2.3 V to 2.7 V 1.5 5.0 9.0 1.5 11.5 ns VCC = 2.7 V 1.5 5.0 8.5 1.5 11.0 ns VCC = 3.0 V to 3.6 V 1.0 4.5 7.5 1.0 9.
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4LVC1G386 NXP Semiconductors 3-input EXCLUSIVE-OR gate Table 9. Measurement points VCC VM Input VI tr = tf 1.65 V to 1.95 V 0.5 × VCC VCC ≤ 2.0 ns 2.3 V to 2.7 V 0.5 × VCC VCC ≤ 2.0 ns 2.7 V 1.5 V 2.7 V ≤ 2.5 ns 3.0 V to 3.6 V 1.5 V 2.7 V ≤ 2.5 ns 4.5 V to 5.5 V 0.5 × VCC VCC ≤ 2.5 ns VEXT VCC VI RL VO G DUT RT CL RL mna616 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance.
PAGE 8
74LVC1G386 NXP Semiconductors 3-input EXCLUSIVE-OR gate 13. Package outline Plastic surface-mounted package; 6 leads SOT363 D E B y X A HE 6 5 v M A 4 Q pin 1 index A A1 1 2 e1 3 bp c Lp w M B e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.30 0.20 0.25 0.10 2.2 1.8 1.35 1.15 1.3 0.65 2.2 2.0 0.45 0.15 0.25 0.15 0.2 0.2 0.
PAGE 9
74LVC1G386 NXP Semiconductors 3-input EXCLUSIVE-OR gate Plastic surface-mounted package (TSOP6); 6 leads D SOT457 E B y A HE 6 X v M A 4 5 Q pin 1 index A A1 c 1 2 3 Lp bp e w M B detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp c D E e HE Lp Q v w y mm 1.1 0.9 0.1 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.
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74LVC1G386 NXP Semiconductors 3-input EXCLUSIVE-OR gate 14. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 12.
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74LVC1G386 NXP Semiconductors 3-input EXCLUSIVE-OR gate 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
PAGE 12
74LVC1G386 NXP Semiconductors 3-input EXCLUSIVE-OR gate 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . .