Datasheet

74LVC2G00 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 12 — 8 April 2013 10 of 20
NXP Semiconductors
74LVC2G00
Dual 2-input NAND gate
Fig 11. Package outline SOT765-1 (VSSOP8)
UNIT
A
1
A
max.
A
2
A
3
b
p
LH
E
L
p
wyv
ceD
(1)
E
(2)
Z
(1)
θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
0.5
3.2
3.0
0.4
0.1
8°
0°
0.13 0.10.20.4
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.40
0.15
Q
0.21
0.19
SOT765-1 MO-187
02-06-07
w M
b
p
D
Z
e
0.12
14
8
5
θ
A
2
A
1
Q
L
p
(A
3
)
detail X
A
L
H
E
E
c
v M
A
X
A
y
2.5 5 mm0
scale
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
1
pin 1 index