Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Gate AND gate 74LVC XSON 8

1. General description

The 74LVC2G08 provides a 2-input AND gate function.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the

74LVC2G08 as a translator in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down applications using I

OFF

. The I

OFF

circuitry disables the output, preventing a damaging backflow current through the device

when it is powered down.

2. Features and benefits

 Wide supply voltage range from 1.65 V to 5.5 V

 5 V tolerant outputs for interfacing with 5 V logic

 High noise immunity

 24 mA output drive (V

=3.0V)

 CMOS low power consumption

 Complies with JEDEC standard:

 JESD8-7 (1.65 V to 1.95 V)

 JESD8-5 (2.3 V to 2.7 V)

 JESD8-B/JESD36 (2.7 V to 3.6 V)

 Latch-up performance exceeds 250 mA

 Direct interface with TTL levels

 Inputs accept voltages up to 5 V

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V

 Multiple package options

 Specified from 40 Cto +85C and 40 Cto+125C

74LVC2G08

Dual 2-input AND gate

Rev. 12 — 2 April 2013 Product data sheet

Summary of content (21 pages)

PAGE 1
74LVC2G08 Dual 2-input AND gate Rev. 12 — 2 April 2013 Product data sheet 1. General description The 74LVC2G08 provides a 2-input AND gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the 74LVC2G08 as a translator in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. 2.
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74LVC2G08 NXP Semiconductors Dual 2-input AND gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC2G08DP 40 C to +125 C TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 74LVC2G08DC 40 C to +125 C VSSOP8 plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.
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74LVC2G08 NXP Semiconductors Dual 2-input AND gate 5. Functional diagram & 1A 1B 2A 2B 1Y & 2Y 001aah789 001aah788 Fig 1. Logic symbol Fig 2. IEC logic symbol A Y B mna221 Fig 3. Logic diagram (one gate) 6. Pinning information 6.1 Pinning 74LVC2G08 1A 1 8 VCC 1B 2 7 1Y 2Y 3 6 2B GND 4 5 2A 74LVC2G08 1A 1 8 VCC 1B 2 7 1Y 2Y 3 6 2B GND 4 5 2A 001aae982 Transparent top view 001aae981 Fig 4.
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74LVC2G08 NXP Semiconductors Dual 2-input AND gate 74LVC2G08 74LVC2G08 1 8 VCC 1B 2 7 1Y 2Y 3 6 2B GND 4 5 2A 1 2B 2A 8 1Y 7 1A 2 6 1B 3 5 2Y GND 4 1A VCC terminal 1 index area 001aai245 Transparent top view Transparent top view Fig 6. 001aae983 Pin configuration SOT996-2 Fig 7. Pin configuration SOT902-2 6.2 Pin description Table 3.
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74LVC2G08 NXP Semiconductors Dual 2-input AND gate 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VI input voltage VO output voltage Conditions Max Unit 0.5 +6.5 V [1] 0.5 +6.5 V [1] 0.5 VCC + 0.5 V [1][2] 0.5 +6.
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74LVC2G08 NXP Semiconductors Dual 2-input AND gate 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 40 C to +85 VIH VIL VOH VOL Conditions Min Typ Max Unit C[1] HIGH-level input voltage LOW-level input voltage VCC = 1.65 V to 1.95 V 0.65  VCC - - V VCC = 2.3 V to 2.7 V 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 4.5 V to 5.5 V 0.7  VCC - - V VCC = 1.
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4LVC2G08 NXP Semiconductors Dual 2-input AND gate Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VOH Conditions Typ Max Unit IO = 100 A; VCC = 1.65 V to 5.5 V VCC  0.1 - - V HIGH-level output voltage VI = VIH or VIL LOW-level output voltage VOL Min IO = 4 mA; VCC = 1.65 V 0.95 - - V IO = 8 mA; VCC = 2.3 V 1.7 - - V IO = 12 mA; VCC = 2.7 V 1.9 - - V IO = 24 mA; VCC = 3.
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74LVC2G08 NXP Semiconductors Dual 2-input AND gate Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9. Symbol Parameter CPD power dissipation capacitance 40 C to +85 C Conditions [3] per gate; VI = GND to VCC [1] Typical values are measured at nominal VCC and at Tamb = 25 C. [2] tpd is the same as tPLH and tPHL [3] 40 C to +125 C Unit Min Typ[1] Max Min Max - 14.
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74LVC2G08 NXP Semiconductors Dual 2-input AND gate VI tW 90 % negative pulse VM 0V VI tf tr tr tf 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC PULSE GENERATOR VI RL VO DUT RT RL CL 001aae235 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance CL = Load capacitance including jig and probe capacitance RT = Termination resistance should be equal to output impedance Zo of the pulse generator VEXT = Test voltage for switching times Fig 9.
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74LVC2G08 NXP Semiconductors Dual 2-input AND gate 13. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm D E A SOT505-2 X c HE y v M A Z 5 8 A A2 (A3) A1 pin 1 index θ Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.00 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.
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74LVC2G08 NXP Semiconductors Dual 2-input AND gate VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D E SOT765-1 A X c y HE v M A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 4 e L detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1 0.15 0.00 0.85 0.60 0.12 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.5 3.2 3.0 0.4 0.40 0.15 0.21 0.19 0.
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74LVC2G08 NXP Semiconductors Dual 2-input AND gate XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm 1 2 SOT833-1 b 4 3 4× (2) L L1 e 8 7 6 e1 5 e1 e1 8× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 2.0 1.9 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2.
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74LVC2G08 NXP Semiconductors Dual 2-input AND gate XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1 x 0.5 mm SOT1089 E terminal 1 index area D A A1 detail X (4×)(2) e L (8×)(2) b 4 5 e1 1 terminal 1 index area 8 L1 X 0 0.5 scale Dimensions Unit mm max nom min 1 mm A(1) 0.5 A1 b D E e e1 L L1 0.35 0.40 0.04 0.20 1.40 1.05 0.15 1.35 1.00 0.55 0.35 0.30 0.35 0.27 0.32 0.12 1.30 0.95 Note 1. Including plating thickness. 2.
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74LVC2G08 NXP Semiconductors Dual 2-input AND gate XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 3 x 2 x 0.5 mm B D SOT996-2 A E A A1 detail X terminal 1 index area e1 1 4 8 5 C C A B C v w b e L1 y y1 C L2 L X 0 1 2 mm scale Dimensions (mm are the original dimensions) Unit(1) mm max nom min A A1 b 0.05 0.35 D E 2.1 3.1 0.5 0.00 0.15 1.9 e e1 0.5 1.5 2.9 L L1 L2 0.5 0.15 0.6 0.3 0.05 0.4 v 0.1 w y 0.05 0.05 y1 0.
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74LVC2G08 NXP Semiconductors Dual 2-input AND gate XQFN8: plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm SOT902-2 X A B D terminal 1 index area E A A1 detail X e v w b 4 3 C C A B C y y1 C 5 e1 2 6 1 7 terminal 1 index area 8 L metal area not for soldering L1 0 1 Dimensions Unit(1) mm max nom min 2 mm scale A 0.5 A1 b D E e e1 0.05 0.25 1.65 1.65 0.20 1.60 1.60 0.55 0.00 0.15 1.55 1.55 0.5 L L1 v 0.35 0.15 0.30 0.10 0.
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74LVC2G08 NXP Semiconductors Dual 2-input AND gate XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.2 x 1.0 x 0.35 mm 1 2 SOT1116 b 4 3 (4×)(2) L L1 e 8 7 e1 6 e1 5 e1 (8×)(2) A1 A D E terminal 1 index area 0 0.5 scale Dimensions Unit mm 1 mm A(1) A1 b D E e e1 max 0.35 0.04 0.20 1.25 1.05 nom 0.15 1.20 1.00 0.55 min 0.12 1.15 0.95 0.3 L L1 0.35 0.40 0.30 0.35 0.27 0.32 Note 1. Including plating thickness. 2.
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74LVC2G08 NXP Semiconductors Dual 2-input AND gate XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1.0 x 0.35 mm SOT1203 b 2 1 3 (4×)(2) 4 L L1 e 8 7 6 e1 e1 5 e1 (8×)(2) A1 A D E terminal 1 index area 0 0.5 scale Dimensions Unit mm 1 mm A(1) A1 b D E e e1 L L1 max 0.35 0.04 0.20 1.40 1.05 0.35 0.40 nom 0.15 1.35 1.00 0.55 0.35 0.30 0.35 min 0.12 1.30 0.95 0.27 0.32 Note 1. Including plating thickness. 2.
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74LVC2G08 NXP Semiconductors Dual 2-input AND gate 14. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC2G08 v.12 20130402 Product data sheet - 74LVC2G08 v.11 Modifications: 74LVC2G08 v.
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74LVC2G08 NXP Semiconductors Dual 2-input AND gate 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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74LVC2G08 NXP Semiconductors Dual 2-input AND gate Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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74LVC2G08 NXP Semiconductors Dual 2-input AND gate 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . .