Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Buffer, driver XSON 6

1. General description

The 74LVC2G17 provides two non-inverting buffers with Schmitt trigger input. It is capable

of transforming slowly changing input signals into sharply defined, jitter-free output

signals.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

devices as translators in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down applications using I

OFF

The I

OFF

circuitry disables the output, preventing the damaging backflow current through

the device when it is powered down.

2. Features and benefits

 Wide supply voltage range from 1.65 V to 5.5 V

 5 V tolerant input/output for interfacing with 5 V logic

 High noise immunity

 Complies with JEDEC standard:

 JESD8-7 (1.65 V to 1.95 V)

 JESD8-5 (2.3 V to 2.7 V)

 JESD-8B/JESD36 (2.7 V to 3.6 V)

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V

 24 mA output drive (V

=3.0V)

 CMOS low-power consumption

 Latch-up performance exceeds 250 mA

 Direct interface with TTL levels

 Multiple package options

 Specified from 40 Cto+85C and 40 Cto+125C

3. Applications

 Wave and pulse shapers for highly noisy environments

74LVC2G17

Dual non-inverting Schmitt trigger with 5 V tolerant input

Rev. 8 — 2 May 2013 Product data sheet

Summary of content (19 pages)

PAGE 1
74LVC2G17 Dual non-inverting Schmitt trigger with 5 V tolerant input Rev. 8 — 2 May 2013 Product data sheet 1. General description The 74LVC2G17 provides two non-inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.
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74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input 4. Ordering information Table 1.
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74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input 1A 1Y 2A 2Y mnb068 Fig 3. Logic diagram 7. Pinning information 7.1 Pinning 74LVC2G17 74LVC2G17 1A 1 6 1A 1 6 1Y GND 2 5 VCC 1Y GND 2 5 VCC 2A 3 4 2Y 2A Pin configuration SOT363 and SOT457 3 4 2Y Fig 5. Pin configuration SOT886 1A 1 6 1Y GND 2 5 VCC 2A 3 4 2Y 001aaf080 001aaf079 Transparent top view Transparent top view 001aaf078 Fig 4. 74LVC2G17 Fig 6.
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74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input 9. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current Conditions VI < 0 V [1] Max Unit 0.5 +6.5 V - 50 mA 0.5 +6.5 V - 50 mA Active mode [1][2] 0.5 VCC + 0.
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74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VOH VI = VT+ or VT HIGH-level output voltage Min Typ Max Unit IO = 100 A; VCC = 1.65 V to 5.5 V VCC  0.1 - - V IO = 4 mA; VCC = 1.65 V 1.2 - - V IO = 8 mA; VCC = 2.3 V 1.9 - - V IO = 12 mA; VCC = 2.7 V 2.
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74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input 12. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter 40 C to +85 C Conditions power dissipation capacitance CPD Unit Min Max Min Max VCC = 1.65 V to 1.95 V 1.5 5.6 10.5 1.5 13.1 ns VCC = 2.3 V to 2.7 V 1.0 3.7 6.5 1.0 8.5 ns VCC = 2.7 V 1.0 3.8 6.5 1.0 8.5 ns VCC = 3.0 V to 3.6 V 1.
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4LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input Table 9. Measurement points Supply voltage Input Output VCC VM VM 1.65 V to 1.95 V 0.5  VCC 0.5  VCC 2.3 V to 2.7 V 0.5  VCC 0.5  VCC 2.7 V 1.5 V 1.5 V 3.0 V to 3.6 V 1.5 V 1.5 V 4.5 V to 5.5 V 0.5  VCC 0.5  VCC VEXT VCC VI RL VO G DUT RT CL RL mna616 Measurement points are given in Table 10. Definitions for test circuit: RL = Load resistance.
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74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input 14. Transfer characteristics Table 11. Transfer characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter positive-going threshold voltage VT+ negative-going threshold voltage VT 40 C to +125 C Unit Min Typ[1] Max Min Max VCC = 1.8 V 0.70 1.10 1.50 0.70 1.70 V VCC = 2.3 V 1.00 1.40 1.80 1.00 2.00 V VCC = 3.0 V 1.30 1.76 2.20 1.
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74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input mnb071 14 ICC (mA) 12 10 8 6 4 2 0 0 0.5 1 1.5 2 VI (V) VCC = 3.0 V. Fig 11. Typical transfer characteristic mnb156 50 ICC (mA) (1) 40 30 20 (2) 10 0 2 3 4 5 VCC (V) 6 (1) Positive-going edge (2) Negative-going edge Linear change of VI between 0.8 V to 2.0 V. All values given are typical unless otherwise specified. Fig 12.
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74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input 16. Package outline Plastic surface-mounted package; 6 leads SOT363 D E B y X A HE 6 5 v M A 4 Q pin 1 index A A1 1 2 e1 3 bp c Lp w M B e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.30 0.20 0.25 0.10 2.2 1.8 1.35 1.15 1.3 0.65 2.2 2.0 0.45 0.15 0.25 0.15 0.2 0.2 0.
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74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input Plastic surface-mounted package (TSOP6); 6 leads D SOT457 E B y A HE 6 5 X v M A 4 Q pin 1 index A A1 c 1 2 3 Lp bp e w M B detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp c D E e HE Lp Q v w y mm 1.1 0.9 0.1 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.
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74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input SOT886 XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm b 1 2 3 4x (2) L L1 e 6 5 e1 4 e1 6x A (2) A1 D E terminal 1 index area 0 1 2 mm scale Dimensions (mm are the original dimensions) Unit mm max nom min A(1) 0.5 A1 b D E 0.04 0.25 1.50 1.05 0.20 1.45 1.00 0.17 1.40 0.95 e e1 0.6 0.5 L L1 0.35 0.40 0.30 0.35 0.27 0.32 Notes 1.
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74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm 1 SOT891 b 3 2 4× (1) L L1 e 6 5 e1 4 e1 6× A (1) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 max b D E e e1 L L1 mm 0.5 0.04 0.20 0.12 1.05 0.95 1.05 0.95 0.55 0.35 0.35 0.27 0.40 0.32 Note 1.
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74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1.0 x 0.35 mm 1 SOT1115 b 3 2 (4×)(2) L L1 e 6 5 4 e1 e1 (6×)(2) A1 A D E terminal 1 index area 0 0.5 scale Dimensions Unit mm 1 mm A(1) A1 b D E e e1 max 0.35 0.04 0.20 0.95 1.05 nom 0.15 0.90 1.00 0.55 min 0.12 0.85 0.95 0.3 L L1 0.35 0.40 0.30 0.35 0.27 0.32 Note 1. Including plating thickness. 2.
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74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1.0 x 0.35 mm 1 SOT1202 b 3 2 (4×)(2) L L1 e 6 5 4 e1 e1 (6×)(2) A1 A D E terminal 1 index area 0 0.5 scale Dimensions Unit mm 1 mm A(1) A1 b D E e e1 L L1 max 0.35 0.04 0.20 1.05 1.05 0.35 0.40 nom 0.15 1.00 1.00 0.55 0.35 0.30 0.35 min 0.12 0.95 0.95 0.27 0.32 Note 1. Including plating thickness. 2.
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74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input 17. Abbreviations Table 12. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 18. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC2G17 v.
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74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input 19. Legal information 19.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
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74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input 21. Contents 1 2 3 4 5 6 7 7.1 7.2 8 9 10 11 12 13 14 15 16 17 18 19 19.1 19.2 19.3 19.4 20 21 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . .