Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Gate OR gate 74LVC XSON 8

1. General description

The 74LVC2G32 provides a 2-input OR gate function.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

devices as translators in a mixed 3.3 V and 5 V environment.

This device is fully speciﬁed for partial power-down applications using I

OFF

. The I

OFF

circuitry disables the output, preventing a damaging backﬂow current through the device

when it is powered down.

2. Features

n Wide supply voltage range from 1.65 V to 5.5 V

n 5 V tolerant outputs in the Power-down mode

n High noise immunity

n ±24 mA output drive (V

= 3.0 V)

n CMOS low power consumption

n Complies with JEDEC standard:

u JESD8-7 (1.65 V to 1.95 V)

u JESD8-5 (2.3 V to 2.7 V)

u JESD8-B/JESD36 (2.7 V to 3.6 V)

n Latch-up performance exceeds 250 mA

n Direct interface with TTL levels

n Inputs accept voltages up to 5 V

n ESD protection:

u HBM EIA/JESD22-A114E exceeds 2000 V

u MM EIA/JESD22-A115-A exceeds 200 V

n Multiple package options

n Speciﬁed from −40 °C to +85 °C and −40 °C to +125 °C

74LVC2G32

Dual 2-input OR gate

Rev. 06 — 27 February 2008 Product data sheet

Summary of content (15 pages)

PAGE 1
74LVC2G32 Dual 2-input OR gate Rev. 06 — 27 February 2008 Product data sheet 1. General description The 74LVC2G32 provides a 2-input OR gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. 2.
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74LVC2G32 NXP Semiconductors Dual 2-input OR gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC2G32DP −40 °C to +125 °C TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 74LVC2G32DC −40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.
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74LVC2G32 NXP Semiconductors Dual 2-input OR gate 6. Pinning information 6.1 Pinning 74LVC2G32 1A 1 8 VCC 1B 2 7 1Y 2Y 3 6 2B GND 4 5 2A 001aab742 Fig 4. Pin configuration TSSOP8 and VSSOP8 74LVC2G32 8 VCC 1B 2 7 1Y 2Y 3 6 2B 1Y 1 2B 2A 8 1 7 1A 2 6 1B 3 5 2Y 4 1A VCC terminal 1 index area 74LVC2G32 4 5 2A GND GND 001aab743 Transparent top view Fig 5. 001aae994 Transparent top view Pin configuration XSON8 Fig 6. Pin configuration XQFN8U 6.
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74LVC2G32 NXP Semiconductors Dual 2-input OR gate 7. Functional description Table 4. Function table [1] Input Output nA nB nY L L L L H H H L H H H H [1] H = HIGH voltage level; L = LOW voltage level. 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VI input voltage VO output voltage Conditions Min Max Unit −0.5 +6.
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74LVC2G32 NXP Semiconductors Dual 2-input OR gate 9. Recommended operating conditions Table 6. Operating conditions Symbol Parameter VCC Conditions Min Max Unit supply voltage 1.65 5.5 V VI input voltage 0 5.5 V VO output voltage Active mode 0 VCC V Power-down mode 0 5.5 V −40 +125 °C VCC = 1.65 V to 2.7 V - 20 ns/V VCC = 2.7 V to 5.5 V - 10 ns/V Tamb ambient temperature ∆t/∆V input transition rise and fall rate 10. Static characteristics Table 7.
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74LVC2G32 NXP Semiconductors Dual 2-input OR gate Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit ICC supply current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A - 0.1 10 µA ∆ICC additional supply current per pin; VI = VCC − 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V - 5 500 µA Ci input capacitance - 2.
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4LVC2G32 NXP Semiconductors Dual 2-input OR gate 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground 0 V); for test circuit see Figure 8. Symbol Parameter −40 °C to +85 °C Conditions Min Max Min Max VCC = 1.65 V to 1.95 V 1.3 3.9 8.8 1.3 11 ns VCC = 2.3 V to 2.7 V 0.8 2.4 4.7 0.8 5.9 ns VCC = 2.7 V 0.8 2.7 4.8 0.8 6.0 ns VCC = 3.0 V to 3.6 V 0.9 2.2 4.2 0.9 5.3 ns VCC = 4.5 V to 5.5 V 0.7 1.7 3.2 0.7 4.
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74LVC2G32 NXP Semiconductors Dual 2-input OR gate Table 9. Measurement points Supply voltage Input Output VCC VM VM 1.65 V to 1.95 V 0.5VCC 0.5VCC 2.3 V to 2.7 V 0.5VCC 0.5VCC 2.7 V 1.5 V 1.5 V 3.0 V to 3.6 V 1.5 V 1.5 V 4.5 V to 5.5 V 0.5VCC 0.5VCC VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC PULSE GENERATOR VI RL VO DUT RT CL RL 001aae235 Test data is given in Table 10.
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74LVC2G32 NXP Semiconductors Dual 2-input OR gate 13. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm D E A SOT505-2 X c HE y v M A Z 5 8 A A2 (A3) A1 pin 1 index θ Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.00 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.
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74LVC2G32 NXP Semiconductors Dual 2-input OR gate VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D E SOT765-1 A X c y HE v M A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 4 e L detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1 0.15 0.00 0.85 0.60 0.12 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.5 3.2 3.0 0.4 0.40 0.15 0.21 0.19 0.
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74LVC2G32 NXP Semiconductors Dual 2-input OR gate XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm 1 2 SOT833-1 b 4 3 4× (2) L L1 e 8 7 6 e1 5 e1 e1 8× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 2.0 1.9 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2.
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74LVC2G32 NXP Semiconductors Dual 2-input OR gate XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm B D SOT902-1 A terminal 1 index area E A A1 detail X L1 e e C ∅v M C A B ∅w M C L 4 y1 C y 5 3 metal area not for soldering e1 b 2 6 e1 7 1 terminal 1 index area 8 X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 b D E e e1 L L1 v w y y1 mm 0.5 0.05 0.00 0.25 0.15 1.65 1.
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74LVC2G32 NXP Semiconductors Dual 2-input OR gate 14. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 12.
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74LVC2G32 NXP Semiconductors Dual 2-input OR gate 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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74LVC2G32 NXP Semiconductors Dual 2-input OR gate 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . .