Datasheet

74LVC2G32_6 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 06 — 27 February 2008 3 of 15
NXP Semiconductors
74LVC2G32
Dual 2-input OR gate
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 4. Pin configuration TSSOP8 and VSSOP8
74LVC2G32
1A V
CC
1B 1Y
2Y 2B
GND 2A
001aab742
1
2
3
4
6
5
8
7
Fig 5. Pin configuration XSON8 Fig 6. Pin configuration XQFN8U
74LVC2G32
2B
1Y
V
CC
2A
2Y
1B
1A
GND
001aab743
36
27
18
45
Transparent top view
001aae994
1B2B
1A
V
CC
2Y
1Y
GND
2A
Transparent top view
3
6
4
1
5
8
7
2
terminal 1
index area
74LVC2G32
Table 3. Pin description
Symbol Pin Description
TSSOP8, VSSOP8 XSON8 XQFN8U
1A 1 1 7 data input
1B 2 2 6 data input
2Y 3 3 5 data output
GND444ground (0 V)
2A 5 5 3 data input
2B 6 6 2 data input
1Y 7 7 1 data output
V
CC
8 8 8 supply voltage