Datasheet

74LVC573A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 19 February 2013 9 of 20
NXP Semiconductors
74LVC573A
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
11. AC waveforms
Measurement points are given in Table 8.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 7. Input (Dn) to output (Qn) propagation delays
mna811
Dn input
Qn output
t
PHL
t
PLH
GND
V
I
V
M
V
M
V
OH
V
OL
Measurement points are given in Table 8.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 8. Latch Enable input (LE) pulse width, the latch enable input to output (Qn) propagation delays
mna812
LE input
Qn output
t
PHL
t
PLH
t
W
1/f
max
V
M
V
OH
V
I
GND
V
OL
V
M