Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Flip-Flop Preset/reset Differential SSOP 14

1. General description

The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs,

clock (nCP) inputs, set (nS

D) and (nRD) inputs, and complementary nQ and nQ outputs.

The set and reset are asynchronous active LOW inputs and operate independently of the

clock input. Information on the data input is transferred to the nQ output on the

LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time

prior to the LOW-to-HIGH clock transition, for predictable operation.

Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and

fall times.

2. Features and benefits

 5 V tolerant inputs for interlacing with 5 V logic

 Wide supply voltage range from 1.2 V to 3.6 V

 CMOS low power consumption

 Direct interface with TTL levels

 Complies with JEDEC standard:

 JESD8-7A (1.65 V to 1.95 V)

 JESD8-5A (2.3 V to 2.7 V)

 JESD8-C/JESD36 (2.7 V to 3.6 V)

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-B exceeds 200 V

 CDM JESD22-C101E exceeds 1000 V

 Specified from 40 C to +85 C and 40 C to +125 C

74LVC74A

Dual D-type flip-flop with set and reset; positive-edge trigger

Rev. 7 — 20 November 2012 Product data sheet

Summary of content (19 pages)

PAGE 1
74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger Rev. 7 — 20 November 2012 Product data sheet 1. General description The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input.
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74LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC74AD 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74LVC74ADB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body width 5.
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74LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger Q C C C C C C D Q C C RD SD mna421 C CP C Fig 4. Logic diagram for one flip-flop 5. Pinning information 14 VCC 1D 2 13 2RD terminal 1 index area 1Q 5 74 11 2CP 12 2D 1SD 4 74 11 2CP 1Q 5 GND(1) 10 2SD 1Q 6 10 2SD 9 1Q 6 9 2Q 8 4 13 2RD 3 GND 7 8 2Q 2Q 1SD 12 2D 2 7 3 1D 1CP GND 1CP 14 VCC 1 1 1RD 1RD 5.
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74LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 5.2 Pin description Table 2.
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74LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current Conditions VI < 0 V [1] VO > VCC or VO < 0 V [2] Min Max Unit 0.5 +6.5 V 50 - mA 0.5 +6.5 V - 50 mA 0.5 VCC + 0.
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74LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 9. Static characteristics Table 7. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions Min HIGH-level input voltage VIH LOW-level input voltage VIL VOH HIGH-level output voltage LOW-level output voltage VOL VCC = 1.2 V Typ[1] 40 C to +125 C Max Min Max Unit 1.08 - - 1.08 - V 0.
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4LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 10. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9. Symbol Parameter tpd propagation delay 40 C to +85 C Conditions 40 C to +125 C Unit Min Typ[1] Max Min Max - 15 - - - ns VCC = 1.65 V to 1.95 V 1.0 5.0 10.3 1.0 11.9 ns VCC = 2.3 V to 2.7 V 1.8 2.9 5.8 1.8 6.7 ns VCC = 2.7 V 1.0 2.7 6.
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74LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9. Symbol Parameter 40 C to +85 C Conditions Min tsu set-up time hold time th maximum frequency fmax tsk(o) CPD [1] Typ[1] Max 40 C to +125 C Unit Min Max nD to nCP; see Figure 7 VCC = 1.65 V to 1.95 V 3.0 - - 3.0 - ns VCC = 2.3 V to 2.7 V 2.5 - - 2.
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74LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 11. AC waveforms VI VM nD input GND th th t su t su 1/fmax VI VM nCP input GND tW t PHL t PLH VOH VM nQ output VOL VOH nQ output VM VOL t PLH t PHL mna422 The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig 7.
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74LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger VI VM nCP input GND t rec VI VM nSD input GND tW tW VI VM nRD input GND t PLH t PHL VOH nQ output VM VOL VOH VM nQ output VOL t PHL t PLH mna423 Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig 8. Table 9.
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74LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC PULSE GENERATOR VI VO DUT RT CL RL 001aaf615 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 9. Table 10.
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74LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 12. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.
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74LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.
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74LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.
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74LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.
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74LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 13. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC74A v.7 20121120 Product data sheet - 74LVC74A v.
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74LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
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74LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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74LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . .