Datasheet

74LVC74A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 20 November 2012 10 of 19
NXP Semiconductors
74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
Measurement points are given in Table 9.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 8. The set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse
widths, and the nRD to nCP recovery time
mna423
t
rec
t
PHL
t
PHL
t
W
t
PLH
t
PLH
V
M
V
M
V
M
t
W
V
M
V
M
V
I
GND
V
I
GND
nSD input
V
I
GND
nRD input
nCP input
V
OH
V
OL
nQ output
V
OH
V
OL
nQ output
Table 9. Measurement points
Supply voltage Input Output
V
CC
V
I
V
M
V
M
1.2 V V
CC
0.5  V
CC
0.5  V
CC
1.65 V to 1.95 V V
CC
0.5  V
CC
0.5  V
CC
2.3 V to 2.7 V V
CC
0.5  V
CC
0.5  V
CC
2.7 V 2.7 V 1.5 V 1.5 V
3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V