Datasheet

74LVC74A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 20 November 2012 7 of 19
NXP Semiconductors
74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
10. Dynamic characteristics
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9.
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
t
pd
propagation
delay
nCP to nQ, nQ; see Figure 7
[2]
V
CC
= 1.2 V - 15 - - - ns
V
CC
= 1.65 V to 1.95 V 1.0 5.0 10.3 1.0 11.9 ns
V
CC
= 2.3 V to 2.7 V 1.8 2.9 5.8 1.8 6.7 ns
V
CC
= 2.7 V 1.0 2.7 6.0 1.0 7.5 ns
V
CC
= 3.0 V to 3.6 V 1.0 2.6 5.2 1.0 6.5 ns
nS
DtonQ, nQ; see Figure 8
V
CC
= 1.2 V - 15 - - - ns
V
CC
= 1.65 V to 1.95 V 0.5 4.0 10.6 0.5 12.2 ns
V
CC
= 2.3 V to 2.7 V 1.0 2.4 6.1 1.0 7.1 ns
V
CC
= 2.7 V 1.0 2.9 6.4 1.0 8.0 ns
V
CC
= 3.0 V to 3.6 V 1.0 2.2 5.4 1.0 7.0 ns
nR
D to nQ, nQ; see Figure 8
V
CC
= 1.2 V - 15 - - - ns
V
CC
= 1.65 V to 1.95 V 0.5 4.1 10.7 0.5 12.4 ns
V
CC
= 2.3 V to 2.7 V 1.0 2.4 6.1 1.0 7.1 ns
V
CC
= 2.7 V 1.0 3.0 6.4 1.0 8.0 ns
V
CC
= 3.0 V to 3.6 V 1.0 2.2 5.4 1.0 7.0 ns
t
W
pulse width clock HIGH or LOW; see Figure 7
V
CC
= 1.65 V to 1.95 V 5.0 - - 5.0 - ns
V
CC
= 2.3 V to 2.7 V 4.0 - - 4.0 - ns
V
CC
= 2.7 V 3.3 - - 4.5 - ns
V
CC
= 3.0 V to 3.6 V 3.3 1.3 - 4.5 - ns
set or reset LOW; see Figure 8
V
CC
= 1.65 V to 1.95 V 5.0 - - 5.0 - ns
V
CC
= 2.3 V to 2.7 V 4.0 - - 4.0 - ns
V
CC
= 2.7 V 3.3 - - 4.5 - ns
V
CC
= 3.0 V to 3.6 V 3.3 1.7 - 4.5 - ns
t
rec
recovery time set or reset; see Figure 8
V
CC
= 1.65 V to 1.95 V 1.5 - - 1.5 - ns
V
CC
= 2.3 V to 2.7 V 1.5 - - 1.5 - ns
V
CC
= 2.7 V 1.5 - - 1.0 - ns
V
CC
= 3.0 V to 3.6 V +1.0 3.0 - 1.0 - ns