Datasheet

74LVCV2G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 29 March 2013 10 of 23
NXP Semiconductors
74LVCV2G66
Overvoltage tolerant bilateral switch
11.1 Waveforms and test circuit
Measurement points are given in Table 10.
Logic levels: V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 11. Input (nY or nZ) to output (nZ or nY) propagation delays
001aaa541
t
PLH
t
PHL
V
M
V
M
V
M
V
M
nY or nZ
input
nZ or nY
output
GND
V
I
V
OH
V
OL
Measurement points are given in Table 10.
Logic levels: V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 12. Enable and disable times
001aaa542
t
PLZ
t
PHZ
switch
disabled
switch
enabled
switch
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
nE input
nY or nZ
nY or nZ
V
I
V
OL
V
OH
V
CC
V
M
V
M
V
X
V
Y
V
M
GND
GND
t
PZL
t
PZH
Table 10. Measurement points
Supply voltage Input Output
V
CC
V
M
V
M
V
X
V
Y
2.3 V to 2.7 V 0.5V
CC
0.5V
CC
V
OL
+0.1V
CC
V
OH
 0.1V
CC
2.7V 1.5V 1.5V V
OL
+0.3V V
OH
 0.3 V
3.0V to 3.6V 1.5V 1.5V V
OL
+0.3V V
OH
 0.3 V
4.5 V to 5.5 V 0.5V
CC
0.5V
CC
V
OL
+0.3V V
OH
 0.3 V