Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Gate AND gate 74VHCT SO 14

1. General description

The 74VHC08; 74VHCT08 are high-speed Si-gate CMOS devices and are pin compatible

with Low-power Schottky TTL (LSTTL). They are speciﬁed in compliance with JEDEC

standard JESD7-A.

The 74VHC08; 74VHCT08 provide the quad 2-input AND function.

2. Features

n Balanced propagation delays

n All inputs have a Schmitt-trigger action

n Inputs accepts voltages higher than V

n Input levels:

u The 74VHC08 operates with CMOS logic levels

u The 74VHCT08 operates with TTL logic levels

n ESD protection:

u HBM JESD22-A114E exceeds 2000 V

u MM JESD22-A115-A exceeds 200 V

u CDM JESD22-C101C exceeds 1000 V

n Multiple package options

n Speciﬁed from −40 °C to +85 °C and from −40 °C to +125 °C

3. Ordering information

74VHC08; 74VHCT08

Quad 2-input AND gate

Rev. 01 — 30 June 2009 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74VHC08D −40 °C to +125 °C SO14 plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

74VHCT08D

74VHC08PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

74VHCT08PW

74VHC08BQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very

thin quad ﬂat package; no leads; 14 terminals;

body 2.5 × 3 × 0.85 mm

SOT762-1

74VHCT08BQ

Summary of content (14 pages)

PAGE 1
74VHC08; 74VHCT08 Quad 2-input AND gate Rev. 01 — 30 June 2009 Product data sheet 1. General description The 74VHC08; 74VHCT08 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard JESD7-A. The 74VHC08; 74VHCT08 provide the quad 2-input AND function. 2.
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74VHC08; 74VHCT08 NXP Semiconductors Quad 2-input AND gate 4. Functional diagram 1 & 3 & 6 2 1 1A 2 1B 4 2A 5 2B 9 3A 10 3B 12 4A 13 4B 1Y 3 4 2Y 6 5 3Y 8 9 A Y & 8 B 10 4Y mna221 11 12 mna222 & 11 13 mna223 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 5. Pinning information 5.
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74VHC08; 74VHCT08 NXP Semiconductors Quad 2-input AND gate 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A 1 data input 1B 2 data input 1Y 3 data output 2A 4 data input 2B 5 data input 2Y 6 data output GND 7 ground (0 V) 3Y 8 data output 3A 9 data input 3B 10 data input 4Y 11 data output 4A 12 data input 4B 13 data input VCC 14 supply voltage 6. Functional description Table 3.
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74VHC08; 74VHCT08 NXP Semiconductors Quad 2-input AND gate Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
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74VHC08; 74VHCT08 NXP Semiconductors Quad 2-input AND gate Table 6. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter VOL 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max LOW-level VI = VIH or VIL output voltage IO = 50 µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 µA; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 3.0 V - - 0.
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74VHC08; 74VHCT08 NXP Semiconductors Quad 2-input AND gate 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure 7. Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max Min Max CL = 15 pF - 4.0 8.8 1.0 10.5 1.0 11.0 ns CL = 50 pF - 5.6 12.3 1.0 14 1.0 15.5 ns - 3.0 5.9 1.0 7.0 1.0 7.5 ns 4.2 7.9 1.0 9.0 1.0 10.0 ns - 10.0 - - - - - pF - 3.2 6.9 1.0 8.0 1.0 9.
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4VHC08; 74VHCT08 NXP Semiconductors Quad 2-input AND gate 11. Waveforms VI VM nA, nB input GND t PHL t PLH VOH VM nY output VOL mna224 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. The input (nA, nB) to output (nY) propagation delays Table 8. Measurement points Type Input Output VM VM 74VHC08 0.5VCC 0.5VCC 74VHCT08 1.5 V 0.5VCC 74VHC_VHCT08_1 Product data sheet © NXP B.V. 2009. All rights reserved.
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74VHC08; 74VHCT08 NXP Semiconductors Quad 2-input AND gate VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC VCC G VI VO RL S1 open DUT RT CL 001aad983 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 7.
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74VHC08; 74VHCT08 NXP Semiconductors Quad 2-input AND gate 12. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.
PAGE 10
74VHC08; 74VHCT08 NXP Semiconductors Quad 2-input AND gate TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.
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74VHC08; 74VHCT08 NXP Semiconductors Quad 2-input AND gate DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b 1 0.05 0.00 0.30 0.18 mm c D (1) Dh E (1) Eh 0.2 3.
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74VHC08; 74VHCT08 NXP Semiconductors Quad 2-input AND gate 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor LSTTL Low-power Schottky Transistor-Transistor Logic ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model CDM Charged Device Model TTL Transistor-Transistor Logic 14. Revision history Table 11.
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74VHC08; 74VHCT08 NXP Semiconductors Quad 2-input AND gate 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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NXP Semiconductors 74VHC08; 74VHCT08 Quad 2-input AND gate 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . .